参数资料
型号: PPC5606BCLU64
厂商: Freescale Semiconductor
文件页数: 66/112页
文件大小: 0K
描述: MCU 32BIT 1M 64MHZ
标准包装: 40
系列: MPC56xx Qorivva
核心处理器: e200z0h
芯体尺寸: 32-位
速度: 64MHz
连通性: CAN,I²C,LIN,SCI,SPI
外围设备: POR,PWM,WDT
输入/输出数: 149
程序存储器容量: 1MB(1M x 8)
程序存储器类型: 闪存
EEPROM 大小: 4K x 16
RAM 容量: 80K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 29x10b,5x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 176-LQFP
包装: 托盘
Electrical characteristics
MPC5607B Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
57
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see
Table 25. Voltage regulator electrical characteristics
Symbol
C
Parameter
Conditions1
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
Value
Unit
Min
Typ
Max
CREGn
SR — Internal voltage regulator external
capacitance
200
500
nF
RREG
SR — Stability capacitor equivalent serial
resistance
Range:
10 kHz to 20 MHz
——
0.2
CDEC1
SR — Decoupling capacitance2 ballast
2 This capacitance value is driven by the constraints of the external voltage regulator supplying the V
DD_BV voltage. A
typical value is in the range of 470 nF.
VDD_BV/VSS_LV pair:
VDD_BV = 4.5 V to 5.5 V
1003
3 This value is acceptable to guarantee operation from 4.5 V to 5.5 V
4704
—nF
VDD_BV/VSS_LV pair:
VDD_BV = 3V to 3.6V
400
CDEC2
SR — Decoupling capacitance regulator
supply
VDD/VSS pair
10
100
nF
VMREG
CC T Main regulator output voltage
Before exiting from reset
1.32
V
P
After trimming
1.16
1.28
IMREG
SR — Main regulator current provided to
VDD_LV domain
——
150
mA
IMREGINT
CC D Main regulator module current
consumption
IMREG = 200 mA
2
mA
IMREG = 0 mA
1
VLPREG
CC P Low-power regulator output voltage
After trimming
1.16
1.28
V
ILPREG
SR — Low-power regulator current provided
to VDD_LV domain
——
15
mA
ILPREGINT
CC D Low-power regulator module current
consumption
ILPREG = 15 mA;
TA = 55 °C
——
600
A
ILPREG = 0 mA;
TA = 55 °C
5—
VULPREG
CC P Ultra low power regulator output
voltage
After trimming
1.16
1.28
V
IULPREG
SR — Ultra low power regulator current
provided to VDD_LV domain
——
5
mA
IULPREGINT CC D Ultra low power regulator module
current consumption
IULPREG = 5 mA;
TA = 55 °C
——
100
A
IULPREG = 0 mA;
TA = 55 °C
2—
IDD_BV
CC D In-rush average current on VDD_BV
during power-up5
——
3006
mA
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