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| 型号： | PSD834F2V |
| 英文描述： | Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM(2M位+256K位双路闪速存储器和64K位静态RAM,闪速PSD,3.3V电源,用于8位MCU.) |
| 中文描述： | 闪光私营部门，3.3V电源，为8位微控制器2兆256千位双闪存和64千位的SRAM（200万位256K位双路闪速存储器和64K的位静态内存，闪速私营部门，3.3V的电源，用于8位微控制器。） |
| 文件页数： | 15/89页 |
| 文件大小： | 522K |
| 代理商： | PSD834F2V |
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PSD834F2V
DETAILED OPERATION
As shown in Figure 2, the PSD consists of six ma-
jor types of functional blocks:
I
Memory Blocks
I
PLD Blocks
I
MCU Bus Interface
I
I/O Ports
I
Power Management Unit (PMU)
I
JTAG Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
MEMORY BLOCKS
The PSD has the following memory blocks:
– Primary Flash memory
– Secondary Flash memory
– SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Primary Flash Memory and Secondary Flash
memory Description
The primary Flash memory is divided evenly into
eight equal sectors. The secondary Flash memory
is divided into four equal sectors. Each sector of
either memory block can be separately protected
from Program and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis. Flash sectorerasure may be suspended
while data is read from other sectors of the block
and then resumed after reading.
During a Program orErase cycle inFlash memory,
the status can be output on Ready/Busy (PC3).
This pin is set upusing PSDsoft Express Configu-
ration.
Memory Block Select Signals
The DPLD generates the Select signals for all the
internal memory blocks (see the section entitled
“PLDs”, on page 27). Each of the eight sectors of
the primary Flash memory has a Select signal
(FS0-FS7) which can contain up to three product
terms. Each of the four sectors of the secondary
Flash memory has a Select signal (CSBOOT0-
CSBOOT3) which can contain up to three product
terms. Having three product terms for each Select
signal allows a given sector tobe mapped in differ-
ent areas of system memory. When using a MCU
with separate Program and Data space, these
flexible Select signals allow dynamic re-mapping
of sectors from one memory space to the other.
Ready/Busy (PC3).
This signal can be used to
output the Ready/Busy status ofthe PSD.The out-
put on Ready/Busy (PC3)is a 0 (Busy) when Flash
memory is being written to,orwhen Flash memory
is being erased. The output is a 1 (Ready) when
no Write or Erase cycle is in progress.
Memory Operation.
The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus Interface. The MCU can ac-
cess these memories in one of two ways:
I
The MCU can execute a typical bus Write or
Read operationjust as it would if accessing a
RAM or ROMdevice using standard bus cycles.
I
The MCU canexecute a specificinstructionthat
consists of several Write and Read operations.
This involves writing specific data patterns to
special addresses within the Flash memory to
invoke an embedded algorithm. These
instructions are summarized in Table 7.
Typically, the MCU can read Flash memory using
Read operations, just as it would read a ROM de-
vice. However, Flash memory can only be altered
using specific Erase and Program instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as it would write a byte to
RAM. To program a byte into Flash memory, the
MCU must execute a Program instruction, then
test the status of the Program cycle. This status
test is achieved by a Read operation or polling
Ready/Busy (PC3).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
相关PDF资料 |
PDF描述 |
|---|---|
| PSD834F2 | Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs(用于8位MCUs的闪速ISP外围) |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD834F2V-15J | 功能描述:CPLD - 复杂可编程逻辑器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD834F2V-15M | 功能描述:CPLD - 复杂可编程逻辑器件 3.0V 2M 150ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD834F2V-20JI | 功能描述:CPLD - 复杂可编程逻辑器件 3.0V 2M 200ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD834F2V-20MI | 功能描述:SPLD - 简单可编程逻辑器件 3.0V 2M 200ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| PSD835G2-70U | 功能描述:静态随机存取存储器 5.0V 4M 70ns RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
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