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参数资料
| 型号： | PSD913F1V-12J |
| 厂商： | 意法半导体 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系统可编程ISP的外设的8位微控制器 |
| 文件页数： | 67/94页 |
| 文件大小： | 476K |
| 代理商： | PSD913F1V-12J |
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Preliminary Information
PSD9XX Family
t A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
Intel 8031, 80196, 80186, 80C251
Motorola 68HC11, 68HC16, 68HC12, and 683XX
Philips 8031 and 8051XA
Zilog Z80, Z8, and Z180
t Internal 1 or 2 Mbit flash memory. This is the main Flash memory. It is divided into
eight equal-sized blocks that can be accessed with user-specified addresses.
t Internal secondary 256 Kbit Flash memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash concurrently.
t 16, 64 or 256 Kbit SRAM. The SRAM’s contents can be protected from a
power failure by connecting an external battery.
t General Purpose PLD (GPLD) with 19 outputs. The GPLD may be used to implement
external chip selects or combinatorial logic function.
t Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
t 27 individually configurable I/O port pins that can be used for the following functions:
MCU I/Os
PLD I/Os
Latched MCU address output
Special function I/Os.
16 of the I/O ports may be configured as open-drain outputs.
t Standby current as low as 50 A for 5 V devices.
t Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the
field.
t Internal page register that can be used to expand the microcontroller address space by
a factor of 256.
t Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD9XX into Power Down Mode.
t Erase/Write cycles:
Flash memory – 100,000 minimum
PLD – 1,000 minimum
Data Retention: 15 years
2.0
Key Features
3
相关PDF资料 |
PDF描述 |
|---|---|
| PSD913F1V-12JI | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12M | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD933212JIT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD933212JT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD933212MT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD913F1V-12JI | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12M | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12MI | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12U | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12UI | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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