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| 型号： | PSD913F1V-12J |
| 厂商： | 意法半导体 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系统可编程ISP的外设的8位微控制器 |
| 文件页数： | 9/94页 |
| 文件大小： | 476K |
| 代理商： | PSD913F1V-12J |
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Preliminary Information
PSD9XX Family
Table 5.
PSD9XX
Pin
Descriptions
(cont.)
Pin Name
Pin*
Type
Description
(PLCC)
PC7
11
I/O
PC7 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. DBE — active-low Data Byte Enable input from 68HC912
type MCUs.
This pin can be configured as a CMOS or Open Drain output.
PD0
10
I/O
PD0 pin of Port D. This port pin can be configured to have
the following functions:
1. ALE/AS input latches address output from the MCU.
2. MCU I/O — write or read from a standard output or input
port.
3. Input to the PLDs.
4. General Purpose PLD output.
PD1
9
I/O
PD1 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. General Purpose PLD output
4. CLKIN — clock input to the automatic power-down
unit’s power-down counter, and the PLD AND array.
PD2
8
I/O
PD2 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. General Purpose PLD output.
4. CSI — chip select input. When low, the MCU can access
the PSD memory and I/O. When high, the PSD memory
blocks are disabled to conserve power.
VCC
15, 38
Power pins
GND
1,16,26
Ground pins
Port A
Port B
Microcontroller
Port A (3:0) Port A (7:4)
Port B (3:0)
Port B (7:4)
8051XA (8-bit)
N/A
Address [7:4]
Address [11:8] N/A
80C251 (page mode)
N/A
Address [11:8] Address [15:12]
All other 8-bit
multiplexed
Address [3:0]
Address [7:4]
Address [3:0]
Address [7:4]
8-bit non-multiplexed
bus
N/A
Address [3:0]
Address [7:4]
Table 6. I/O Port Latched Address Output Assignments*
N/A = Not Applicable
**Refer to the I/O Port Section on how to enable the Latched Address Output function.
*The pin numbers in this table are for the PLCC package only. See the package information section for pin
numbers on other package types.
13
相关PDF资料 |
PDF描述 |
|---|---|
| PSD913F1V-12JI | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12M | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD933212JIT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD933212JT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD933212MT | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD913F1V-12JI | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12M | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12MI | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12U | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F1V-12UI | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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