参数资料
型号: PSD935F1-B-90B81
厂商: 意法半导体
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述: 在8片位微控制器可配置存储系统
文件页数: 51/91页
文件大小: 488K
代理商: PSD935F1-B-90B81
PSD9XX Family
PSD935G2
54
The
PSD935G2
Functional
Blocks
(cont.)
INTERNAL
DATA
BUS
DATA OUT
REG.
DQ
D
G
Q
DQ
WR
ADDRESS
ALE
READ MUX
P
D
B
CONTROL REG.
DIR REG.
PLD INPUT (PORT F)
ISP OR BATTERY BACK-UP (PORT E)
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
ADDRESS
A[ 7:0] OR A[15:8]
CONFIGURATION
BIT
Figure 23. Ports E, F and G Structure
9.4.8 Port F – Functionality and Structure
Port F can be configured to perform one or more of the following functions:
t MCU I/O Mode
t PLD Input – as direct input ot the PLD array.
t Address In – additional high address inputs. Direct input to the PLD array.
t Latched Address Out – Provide latched address out per Table 18.
t Slew Rate – pins can be set up for fast slew rate.
t Data Port – connected to D[7:0] when Port F is configured as Data Port for a
non-multiplexed bus.
9.4.9 Port G – Functionality and Structure
Port G can be configured to perform one or more of the following functions:
t MCU I/O Mode
t Latched Address Out – Provide latched address out per Table 18.
t Open Drain – pins can be configured in Open Drain Mode
相关PDF资料
PDF描述
PSD935F1-B-90B81I Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 20pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: 100% Tin (Sn); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate
PSD935F1-B-90J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F1-B-90JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F1-B-90M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F1-B-90MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
相关代理商/技术参数
参数描述
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