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参数资料
型号： PSD935F1-B-90B81
厂商： 意法半导体
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存储系统
文件页数： 58/91页
文件大小： 488K
代理商： PSD935F1-B-90B81
PSD9XX Family
PSD935G2
60
The
PSD935G2
Functional
Blocks
(cont.)
9.5.3 Reset and Power On Requirement
9.5.3.1 Power On Reset
Upon power up the PSD935G2 requires a reset pulse of tNLNH-PO (minimum 1 ms) after
VCC is steady. During this time period the device loads internal configurations, clears
some of the registers and sets the Flash into operating mode. After the rising edge of
reset, the PSD935G2 remains in the reset state for an additional tOPR (maximum 120 ns)
nanoseconds before the first memory access is allowed.
The PSD935G2 Flash memory is reset to the read array mode upon power up. The FSi
and CSBOOTi select signals along with the write strobe signal must be in the false
state during power-up reset for maximum security of the data contents and to remove
the possibility of data being written on the first edge of a write strobe signal. Any Flash
memory write cycle initiation is prevented automatically when VCC is below VLKO.
9.5.3.2 Warm Reset
Once the device is up and running, the device can be reset with a much shorter pulse of
tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
after warm reset. Figure 26 shows the timing of the power on and warm reset.
OPERATING LEVEL
POWER ON RESET
VCC
RESET
t NLNH–PO
t OPR
t NLNH-A
t NLNH
t OPR
WARM
RESET
Figure 26. Power On and Warm Reset Timing
9.5.3.3
I/O Pin, Register and PLD Status at Reset
Table 28 shows the I/O pin, register and PLD status during power on reset, warm reset
and power down mode. PLD outputs are always valid during warm reset, and they are
valid in power on reset once the internal PSD configuration bits are loaded. This loading of
PSD is completed typically long before the VCC ramps up to operating level. Once the PLD
is active, the state of the outputs are determined by the equations specified in PSDsoft.
相关PDF资料
PDF描述
PSD935F1-B-90B81I Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 20pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: 100% Tin (Sn); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate
PSD935F1-B-90J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F1-B-90JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F1-B-90M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F1-B-90MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
相关代理商/技术参数
参数描述
PSD935G2-90U 功能描述:SPLD - 简单可编程逻辑器件 TQFP-80 5V 4M 90N RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD935G2V-90U 功能描述:SPLD - 简单可编程逻辑器件 U 511-PSD835G2V-90U RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD954F2-90J 功能描述:SPLD - 简单可编程逻辑器件 U 511-PSD854F2-90J RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD954F2-90M 功能描述:SPLD - 简单可编程逻辑器件 U 511-PSD854F2-90M RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
PSD954F2V-90J 功能描述:SPLD - 简单可编程逻辑器件 5.0V 2M 90ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24
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