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参数资料
| 型号： | PT7A6526 |
| 英文描述： | 50V Fast Recovery Diode in a DO-203AB (DO-5) package |
| 中文描述： | 单通道协议控制器？ |用户手册PT7A6525（6）在中断演示模式？（PDF格式系统） |
| 文件页数： | 34/41页 |
| 文件大小： | 1640K |
| 代理商： | PT7A6526 |
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4
PT Pericom Technology Inc.
The Demo Board of PT7A6525
in DMA Mode
Introduction
This application note provides a simplified application
of PT7A6525 in DMA mode. DMA mode provides
higher data block transfer rate between PT7A6525
HDLC channel and system memory, and needs less
CPU control in data block transferring than in Inter-
rupt Request mode.
In DMA mode, the circuit designment is more com-
plex. This demo board shows a typical circuit which
can implement the fundamental functions of DMA in-
terface in an application system.
This application mainly describes the function block
of the demo board and the principle of PT7A6525
DMA interface, which includes the DMA transferring
process of PT7A6525, the programming of DMA con-
troller and PT7A6525, and the program flow of CPU
to implement the transmitting or receiving process of a
HDLC frame.
This application note provides the User Manual of the
demo program, too.
Function Description
Figure 2 shows the function block diagram of the demo
board of PT7A6525 in DMA mode. The figure shows
the main function block and some important signals
between them.
According to Figure 2, the function blocks connected
to system bus respectively. There are some other sig-
nals to implement control function. Because the CPU
is MC68HC000, which is a 16-bit microprocessor, the
width of the databus in system bus is 16-bit. The con-
trol bus is in Intel Bus Mode, so the control signals of
MC68HC000 can not connect to system bus directly.
The EPLD adapts these signals.
The principles of the function blocks will be described
in the following parts.
PT7A6525
CPU
DMA
Controller
Clock
RAM
ROM
System Bus
INT
DREQ
DACK
EPLD
Control
Signals
RS232
Interface
To PC
TxD
RxD
Figure 2. Function Block Diagram
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