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参数资料
| 型号： | PT7A6526 |
| 英文描述： | 50V Fast Recovery Diode in a DO-203AB (DO-5) package |
| 中文描述： | 单通道协议控制器？ |用户手册PT7A6525（6）在中断演示模式？（PDF格式系统） |
| 文件页数： | 38/41页 |
| 文件大小： | 1640K |
| 代理商： | PT7A6526 |
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6
PT Pericom Technology Inc.
The Demo Board of PT7A6525
in DMA Mode
Clock
The clock circuit is shown in Appendix A, Schematics
4. The 20MHz clock and PT7A4402 (or PT7A4401)
provide clock signals for MC68HC000, PT7A6525 and
8237. The MC68HC000 master clock is 10MHz. And
PT7A4402 provided 8KHz frame pulse, 4.096MHz
clock and 1.544MHz clock.
PT7A6525 (or PT7A6526)
PT7A6525 is designed to implement high-speed com-
munication links using HDLC protocols. It has two
completely independent full-duplex HDLC channels
(Channel A and Channel B), while PT7A6526 supports
only one (Channel B). Associated with each serial chan-
nel there are a set of independent command and status
registers and 64-byte FIFOs. Data blocks from/to sys-
tem memory can be transferred by either Interrupt Re-
quest or Direct Memory Access (DMA).
For each channel of PT7A6525/PT7A6526, there are
two DMA interface. So PT7A6525 contains a 4-chan-
nel DMA interface, while PT7A6526 contains a 2-
channnel DMA interface.
For each channel, a separate DMA Request output for
the Transmit (DRQT) and Receive direction (DRQR),
and a DMA Acknowledgment (DACK) for both direc-
tions are provided.
As long as data transfers from/to the specific FIFO are
needed, PT7A6525 activates the DRQ lines. It deacti-
vates the DRQ lines immediately after the last read/
write cycle of the data transfer has started. If the DMA
controller is in Level-Triggered Demand Transfer Mode,
it executes the correct number of bus cycles by watch-
ing the DRQ. Read cycles will be executed if DMA
controller is requested by DRQR and write cycles will
be executed if DMA controller is requested by DRQT.
If a DMA acknowledgment signal provided by the
DMA controller is connected to the DACK pin of
PT7A6525, PT7A6525 can be accessed as an external
I/O device. The address and chip-select signal (CS) are
not needed, and the top byte of the FIFO is read/writ-
ten in each bus cycle. If DACK is not provided, memory-
memory transfer must be performed, and chip-select
and address are needed.
In DMA mode, the bit D7 of XBCH register must be
set. The length of the next frame to be transmitted must
be written into XBCH and XBCL before transmitting.
And the length of the last received frame can be read
from RBCH and RBCL. The detail can be seen from
PT7A6525 datasheet.
The circuit of PT7A6525 is shown in Appendix A, Sche-
matics 3.
DMA Controller
The D8237AC-5 is used in this demo board as the DMA
controller. It is compatible with Intel 8237A-5. It pro-
vide four independent programmable DMA channels.
The circuit of 8237 is shown in Appendix A, Schemat-
ics 3. In this demo board, channel 0 serves for the Re-
ceiver of Channel B of PT7A6525 and channel 1 for
the Transmitter of Channel B of PT7A6525.
When 8237 works in active cycles, it controls the sys-
tem bus. 8237 has 8-bit data lines and A0-A7 address
bus, and the A8-A15 are multiplexed on the data lines.
If A8-A15 is used, an external 8-bit address latch is
needed to generate 16-bit address bus. In order to sim-
plify the circuit design, only A0-A7 is used in this demo
board. So the active address range is 0 to FFh in DMA
transferring process. Because in this demo board trans-
mitting and receiving buffer share the same RAM area
in the UT6264 connected to D0~D7, the length of a
frame transmitted/received must be less than 128.
There are four independent DMA channel in 8237. Each
channel has a set of registers including Current Ad-
dress Register, Current Word Count Register, Base
Address Register and Base Word Count Register. Be-
fore a DMA process, the Base Address Register and
Base Word Count Register should be set. The values of
the registers in 8237 will be discussed in the following
parts.
8237 has some registers such as Mode Register,
Command Register, Mask Register, etc. The details can
be seen from its Datasheet. Some of these register are
initialized in Demo Program.
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相关代理商/技术参数 |
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| PT7A6527 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Quad-channel Protocol Controller? | Demo board Schematic and Program?(PDF) |
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