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参数资料
| 型号： | PT7A6526 |
| 英文描述： | 50V Fast Recovery Diode in a DO-203AB (DO-5) package |
| 中文描述： | 单通道协议控制器？ |用户手册PT7A6525（6）在中断演示模式？（PDF格式系统） |
| 文件页数： | 41/41页 |
| 文件大小： | 1640K |
| 代理商： | PT7A6526 |
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9
PT Pericom Technology Inc.
The Demo Board of PT7A6525
in DMA Mode
The Programming of DMA Controller and
PT7A6525
8237 and PT7A6525 can be programmed by writing
their registers. In this demo board, all the content of
registers are written by Demo Program via the CPU on
the demo board. The details of the definitions of these
registers , such as address and bit definition, can be
found in 8237 datasheet or PT7A6525 datasheet.
Initialization
To initialize 8237 in the correct status, Command Reg-
ister, Mode Register, Mask Register and some other
registers needs to be written by Demo Program. Demo
Program writes the contents of some registers of 8237
before or after each DMA transferring process, too.
PT7A6525 is initiated when Demo Program begins,
too.
Table 2 shows the initialization process of 8237 in Demo
Program. It shows the content of the register.
Table 2. Initialization of 8237
Step
Register
Content
1
Command
04h
2
Master Clear
3
Base Address of
Channel 0
(Low byte)
00h
4
Base Address of
Channel 0
(High byte)
00h
5
Base Word Count
of Channel 0
(Low byte)
7Fh
6
Base Word Count
of Channel 0
(High byte)
00h
7
Base Address
of Channel 1
(Low byte)
80h
8
Base Address
of Channel 1
(High byte)
00h
Step
Register
Content
9
Mode
14h
10
Mode
19h
11
Mode
16h
12
Mode
1Bh
13
Command
10h
14
Mask
00h
15
Mask
01h
After the initialization, 8237 is enabled. Channel 0 (for
Receiver of Channel B of PT7A6525) is in Read Trans-
fer Mode. Channel 1 (for Transmitter of Channel B of
PT7A6525) is in Write Transfer Mode. Channel 2 and
Channel 3 are masked. The limit of the length of data
is 128 (7Fh+1). And the reading buffer and the writing
buffer in system memory are independent. The DMA
priority is in Rotating mode. All the four channels are
Autoinitialization Enable. Thus they needn’t to be re-
started after a transfer. Because the EOP is not pro-
vided in this demo board by hardware, the Demo Pro-
gram must initiate the Base Address register and Base
Word Count register of Channel 0 again after each DMA
transfer. After a frame transmission, the word count
decreases to FFFFh, so a internal EOP in 8237 is gen-
erated. This EOP restores the correct Base Address (so
the re-initialization of this register is not needed), but
the Base Word Count must be written to fit to the length
of the next frame before the next transmission.
The initialization of PT7A6525 setups the contents of
some registers. This initialization process will be shown
in the User Manual of the Demo Program. The register
contents are shown in Figure 10. After Initialization,
the PT7A6525 works in Transparent Mode, Clock Mode
0. Channel B is in DMA Transmission Mode, while
Channel A is in Interrupt Transmission Mode. The de-
tails of the registers can be seen from PT7A6525
datasheet.
The registers can be set as other values if PT7A6525 is
needed to work in other modes.
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