参数资料
型号: PTN3392BS/FX
厂商: NXP SEMICONDUCTORS
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PQCC48
封装: 7 X 7 MM, 0.85 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, MO-220, SOT619-1, HVQFN-48
文件页数: 26/29页
文件大小: 641K
代理商: PTN3392BS/FX
PTN3392
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 July 2010
6 of 29
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
[1]
HVQFN48 package die supply ground is connected to both GND pins and exposed center pad. GND pins
7, 23, 28, 29, 41, 45, 48, and exposed center pad must be connected to supply ground for proper device
operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction
through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
Strap pins, S[3:0]
S0
33
input
Open (internal pull-down) = logic 0:
Implement VGA-side monitor detect
according to VESA DisplayPort Standard
v1.1a sections 7 and 8 (Ref. 1). Refer to
Section 7.4.1 for S0 = 0 behavior.
HIGH (external pull-up) = logic 1:
Set HPD HIGH upon VGA monitor
detection; set HPD LOW upon VGA monitor
detachment. Refer to Section 7.4.2 for
S0 = 1 behavior.
Default S0 = 0 for standard compliance.
S1
34
input
reserved; leave open-circuit (default internal
pull-down)
S2
35
input
Open (internal pull-down) = logic 0 to set
default I2C speed to 100 kbit/s.
HIGH (external pull-up) = logic 1, to set
default I2C speed to 10 kbit/s.
This pin may be left open-circuit (internal
pull-down) or tied to VDD according to the
desired default I2C speed. See more
explanation in Table 3 about S2 pin setting
and DPCD register 00109h.
S3
36
input
reserved; leave open-circuit (default internal
pull-down)
Miscellaneous
RESET_N
1
input
Hardware reset input (active LOW); internal
pull-up. A capacitor must be connected
between this pin and ground. A 1
μF capacitor
is recommended.
CLK_O
2
output
DisplayPort receiver test clock output
LDOCAP_CORE 30
power
1.8 V digital core supply decoupling
OSC_IN
26
input
crystal oscillator input
OSC_OUT
27
output
crystal oscillator output
LDOCAP_AUX
38
power
1.8 V AUX supply decoupling
RRX
42
input
Receiver termination resistance control. A
12 k
Ω resistor must be connected between
this pin and LDOCAP_AUX (pin 38).
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
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