参数资料
型号: PTN3392BS/FX
厂商: NXP SEMICONDUCTORS
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PQCC48
封装: 7 X 7 MM, 0.85 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, MO-220, SOT619-1, HVQFN-48
文件页数: 28/29页
文件大小: 641K
代理商: PTN3392BS/FX
PTN3392
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 July 2010
8 of 29
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
7.3 DPCD registers
DPCD registers that are part of the VESA DisplayPort v1.1a are described in detail in
Ref. 1. The following paragraphs only describe the specific implementation by PTN3392.
The PTN3392 DisplayPort receiver capability and status information about the link are
reported by DisplayPort Configuration Data (DPCD) registers, when a DisplayPort source
issues a read command on the AUX CH. The DisplayPort source device can also write to
the link configuration field of DPCD to configure and initialize the link. The DPCD is
DisplayPort v1.1a compliant.
It is the responsibility of the host to only issue commands within the capability of the
PTN3392 as defined in the ‘Receiver Capability Field’ in order to prevent undefined
behavior. PTN3392 specific DPCD registers are listed in Table 3.
7.3.1 PTN3392 specific DPCD register settings
Table 3.
PTN3392 specific DPCD registers
DPCD
register [1]
Description
Power-on
Reset
value
Read/write
over
AUX CH
Receiver Capability Field
0000Bh
RECEIVE_PORT1_CAP_1. ReceiverPort1 Capability_1.
00h
read only
0000Ch
I2C-bus speed control capabilities bit map. The bit values in
this register are assigned to I2C-bus speeds as follows:
Bits 7:0
0000 0001b = 1 kbit/s; supported by PTN3392
0000 0010b = 3 kbit/s; supported by PTN3392
0000 0100b = 10 kbit/s; supported by PTN3392
0000 1000b = 100 kbit/s; supported by PTN3392
0001 0000b = 400 kbit/s; not supported by PTN3392
0010 0000b = 1 Mbit/s; not supported by PTN3392
0100 0000b = reserved
1000 0000b = reserved
0Fh
read only
Link Configuration Field
00109h
I2C-bus speed control/status bit map.
Bit values in this register are assigned to I2C-bus speeds
as follows:
Bits 7:0
0000 0001b = 1 kbit/s; supported by PTN3392
0000 0010b = 3 kbit/s; supported by PTN3392
0000 0100b = 10 kbit/s; supported by PTN3392
0000 1000b = 100 kbit/s; supported by PTN3392
0001 0000b = 400 kbit/s; not supported by PTN3392
0010 0000b = 1 Mbit/s; not supported by PTN3392
0100 0000b = reserved
1000 0000b = reserved
Default value: 0000 1000b (100 kbit/s)
See also behavior of pin S2 in Table 2.
S2 setting
read/write
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