15
QL5432 - QuickPCI
TM
Pin/Bus Name
Type
Function
AD[31:0]
CBEN[3:0]
T/S
T/S
PCI Address and Data: 32 bit multiplexed address/data bus.
PCI Bus Command and Byte Enables: Multiplexed bus which contains byte
enables for AD[31:0] or the Bus Command during the address phase of a
PCI transaction.
PCI Parity: Even Parity across AD[31:0] and C/BEN[3:0] busses. Driven
one clock after address or data phases. Master drives PAR on address cycles
and PCI writes. The Target drives PAR on PCI reads.
PCI Cycle Frame: Driven active by current PCI Master during a PCI transac-
tion. Driven low to indicate the address cycle, driven high at the end of the
transaction.
PCI Device Select. Driven by a Target that has decoded a valid base address.
PCI System Clock Input.
PCI System Reset Input
PCI Request. Indicates to the Arbiter that this PCI Agent (Initiator) wishes to
use the bus. A point to point signal between the PCI Device and the System
Arbiter.
PCI Grant. Indicates to a PCI Agent (Initiator) that it has been granted access
to the PCI bus by the Arbiter. A point to point signal between the PCI device
and the System Arbiter.
PCI Data Parity Error. Driven active by the initiator or target two clock cycles
after a data parity error is detected on the AD and C/BE# busses.
PCI System Error: Driven active when an address cycle parity error, data par-
ity error during a special cycle, or other catastrophic error is detected.
PCI Initialization Device Select. Use to select a specific PCI Agent during
System Initialization.
PCI Initiator Ready. Indicates the Initiator’s ability to complete a read or
write transaction. Data transfer occurs only on clock cycles where both
IRDYN and TRDYN are active.
PCI Target Ready. Indicates the Target’s ability to complete a read or write
transaction. Data transfer occurs only on clock cycles where both IRDYN
and TRDYN are active.
PCI Stop. Used by a PCI Target to end a burst transaction.
Interrupt A. Asynchronous Active-Low Interrupt Request.
PAR
T/S
FRAMEN
S/T/S
DEVSELN
CLK
RSTN
REQN
S/T/S
IN
IN
T/S
GNTN
IN
PERRN
S/T/S
SERRN
O/D
IDSEL
IN
IRDYN
S/T/S
TRDYN
S/T/S
STOPN
INTAN
S/T/S
O/D
QL5432 External Device Pins