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参数资料
| 型号： | QL5432-33APB456I |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 6/20页 |
| 文件大小： | 559K |
| 代理商： | QL5432-33APB456I |
6
Preliminary
QL5432 - QuickPCI
TM
6
Mst_IRDYN
O
Copy of the PCI IRDYN signal generated by QL5x33 as PCI master. Valid only when QL5x33 is the PCI mas-
ter. Kept low otherwise. Not usually used in the back-end design.
Target abort detected during master transaction. This is normally an error condition to be handled in the DMA
controller.
Target timeout detected (no response from target). This is normally an error condition to be handled in the
DMA controller.
Mst_Tabort_Det
O
Mst_TTO_Det
O
Usr_Addr_WrData[31:0]
O
Target address, and target write data. During all target accesses, the address is presented on
Usr_Addr_WrData[31:0] at the same time Usr_Adr_Valid is active. During target write transactions, this
port also presents valid write data to the PCI configuration space or user logic when Usr_Adr_Inc is
active.
PCI command and byte enables. During target accesses, the PCI command is presented on Usr_CBE[3:0]
at the same time Usr_Adr_Valid is active. This port also presents active-low byte enables to the PCI con-
figuration space or user logic.
Indicates the beginning of a PCI transaction, and that a target address is valid on Usr_Addr_WrData[31:0]
and the PCI command is valid on Usr_CBE[3:0]. When this signal is active, the target address must be
latched and decoded to determine if this address belongs to the device's memory or I/O space. Also, the
PCI command must be decoded to determine the type of PCI transaction. On subsequent clocks of a tar-
get access, this signal is low, indicating that address is NOT present on Usr_Addr_WrData[31:0].
Indicates that the target address should be incremented, because the previous data transfer has com-
pleted. During burst target accesses, the target address is only presented to the back-end logic at the
beginning of the transaction (when Usr_Adr_Valid is active), and must therefore be latched and incre-
mented (by 4) for subsequent data transfers. Note that during target write transactions, Usr_Adr_Inc indi-
cates valid data on Usr_Addr_WrData[31:0] that must be accepted by the backend logic (regardless of the
state of Usr_Rdy). During read transactions, Usr_Adr_Inc signals to the backend that the PCI core has
presented the read data on the PCI bus (TRDYN asserted).
This signal should be the combinatorial decode of the "user read" command from Usr_CBE[3:0]. This
command may be mapped from any of the PCI "read" commands, such as Memory Read, Memory Read
Line, Memory Read Multiple, I/O Read, etc. It is internally gated with Usr_Adr_Valid.
This signal should be the combinatorial decode of the "user write" command from Usr_CBE[3:0]. This
command may be mapped from any of the PCI "write" commands, such as Memory Write or I/O Write. It
is internally gated with Usr_Adr_Valid.
This signal should be driven active when the address on Usr_Addr_WrData[31:0] has been decoded and
determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be compared to
each of the valid Base Address Registers in the PCI configuration space. Also, this signal must be gated by
the Memory Access Enable or I/O Access Enable registers in the PCI configuration space (Command
Register bits 1 or 0 at offset 04h). Internally gated with Usr_Adr_Valid.
This signal is active throughout a "user write" transaction, which has been decoded by Usr_WrDecode at
the beginning of the transaction. The write strobe for individual DWORDs of data (on
Usr_Addr_WrData[31:0]) during a user write transaction should be generated by logically ANDing this sig-
nal with Usr_Adr_Inc.
This signal is active throughout a "configuration write" transaction. The write strobe for individual
DWORDs of data (on Usr_Addr_WrData[31:0]) during a configuration write transaction should be gener-
ated by logically ANDing this signal with Usr_Adr_Inc.
This signal is active throughout a "user read" transaction, which has been decoded by Usr_RdDecode at
the beginning of the transaction.
This signal is active throughout a "configuration read" transaction.
Data from the PCI configuration registers, required to be presented during PCI configuration reads.
Data from the back-end user logic, required to be presented during PCI user reads.
Usr_CBE[3:0]
O
Usr_Adr_Valid
O
Usr_Adr_Inc
O
Usr_RdDecode
I
Usr_WrDecode
I
Usr_Select
I
Usr_Write
O
Cfg_Write
O
Usr_Read
O
Cfg_Read
Cfg_RdData[31:0]
Usr_RdData[31:0]
O
I
I
PCI Target Interface
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相关代理商/技术参数 |
参数描述 |
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| QL5432-33APQ208C-5846 | 制造商:QuickLogic Corporation 功能描述: |
| QL55M6XD30BQ | 制造商:Banner Engineering 功能描述:QL55M6XD30BQ LUMINESCENCE NPN/PNP M12 20 TO 40mm |
| QL55M6XD50BQ | 制造商:Banner Engineering 功能描述:QL55M6XD50BQ LUMINESCENCE NPN/PNP M12 40 TO 75mm |
| QL564 | 制造商:Aim & Thurlby Thandar Instruments 功能描述:PSU 56V 4A PECISION |
| QL564 SII | 制造商:Aim & Thurlby Thandar Instruments 功能描述:POWER SUPPLY, BENCH, ADJ, 1O/P, 56V, Power Supply Output Type:Adjustable, No. of Outputs:1, Output Voltage Min:0V, Output Voltage Max:56V, Output Current Min:0A, Output Current Max:4A, Power Rating:112W, Input Voltage:115VAC / 230VAC, RoHS Compliant: NA 制造商:TTI (THURLBY THANDAR INSTRUMENTS) 功能描述:POWER SUPPLY, BENCH, ADJ, 1O/P, 56V, Power Supply Output Type:Adjustable, No. of |
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