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参数资料
| 型号： | QL5432-33APB456I |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 8/20页 |
| 文件大小： | 559K |
| 代理商： | QL5432-33APB456I |
8
Preliminary
QL5432 - QuickPCI
TM
8
The QL5432 device has twenty 1,152-bit RAM mod-
ules, for a total of 23,040 RAM bits. Using two
“mode” pins, designers can configure each module
into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2
blocks. See the figure below. The blocks are also
easily cascadable to increase their effective width or
depth.
The RAM modules are “dual-ported”, with com-
pletely independent READ and WRITE ports and
separate READ and WRITE clocks. The READ ports
support asynchronous and synchronous operation,
while the WRITE ports support synchronous opera-
tion. Each port has 18 data lines and 9 address lines,
allowing word lengths of up to 18 bits and address
spaces of up to 512 words. Depending on the mode
selected, however, some higher order data or address
lines may not be used.
The Write Enable (WE) line acts as a clock enable for
synchronous write operation. The Read Enable (RE)
acts as a clock enable for synchronous READ opera-
tion (ASYNCRD input low), or as a flow-through
enable for asynchronous READ operation (ASYN-
CRD input high).
Designers can cascade multiple RAM modules to
increase the depth or width allowed in single modules
by connecting corresponding address lines together
and dividing the words between modules. This
approach allows up to 512-deep configurations as
large as 40 bits wide in the QL5432 device.
A similar technique can be used to create depths
greater than 512 words. In this case address signals
higher than the eighth bit are encoded onto the write
enable (WE) input for WRITE operations. The READ
data outputs are multiplexed together using encoded
higher READ address bits for the multiplexer
SELECT signals.
FIGURE 4: RAM Module
JTAG pins support IEEE standard 1149.1a to pro-
vide boundary scan capability for the QL5432
device. Six pins are dedicated to JTAG and program-
ming functions on each QL5432 device, and are
unavailable for general design input and output sig-
nals. TDI, TDO, TCK, TMS, and TRSTB are JTAG
pins. A sixth pin, STM, is used only for program-
ming.
RAM Module Features
Address Buses [a:0]
[5:0]
[6:0]
[7:0]
[8:0]
Data Buses [w:0]
[17:0]
[8:0]
[3:0]
[1:0]
64x18
128x9
256x4
512x2
MODE[1:0]
WA[a:0]
WD[w:0]
WE
WCLK
RAM Module
ASYNCRD
RA[a:0]
RD[w:0]
RE
RCLK
JTAG Support
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相关代理商/技术参数 |
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| QL5432-33APQ208C-5846 | 制造商:QuickLogic Corporation 功能描述: |
| QL55M6XD30BQ | 制造商:Banner Engineering 功能描述:QL55M6XD30BQ LUMINESCENCE NPN/PNP M12 20 TO 40mm |
| QL55M6XD50BQ | 制造商:Banner Engineering 功能描述:QL55M6XD50BQ LUMINESCENCE NPN/PNP M12 40 TO 75mm |
| QL564 | 制造商:Aim & Thurlby Thandar Instruments 功能描述:PSU 56V 4A PECISION |
| QL564 SII | 制造商:Aim & Thurlby Thandar Instruments 功能描述:POWER SUPPLY, BENCH, ADJ, 1O/P, 56V, Power Supply Output Type:Adjustable, No. of Outputs:1, Output Voltage Min:0V, Output Voltage Max:56V, Output Current Min:0A, Output Current Max:4A, Power Rating:112W, Input Voltage:115VAC / 230VAC, RoHS Compliant: NA 制造商:TTI (THURLBY THANDAR INSTRUMENTS) 功能描述:POWER SUPPLY, BENCH, ADJ, 1O/P, 56V, Power Supply Output Type:Adjustable, No. of |
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