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参数资料
| 型号： | QL6250 |
| 厂商： | QuickLogic Corp. |
| 英文描述： | Eclipse Family Combining Performance, Density, and Embedded RAM(Eclipse 系列性能、密度和嵌入式相结合的RAM) |
| 中文描述： | Eclipse的家庭结合性能，密度，和嵌入式内存（Eclipse的系列性能，密度和嵌入式相结合的内存） |
| 文件页数： | 10/12页 |
| 文件大小： | 258K |
| 代理商： | QL6250 |
5-10
Preliminary
Eclipse
I/O Control and Local Hi-Drives
Each bank of I/O
’
s has 2 input only pins that can be
programmed to drive the RST, CLK and EN inputs of
I/O
’
s in that bank. These input only pins also double
up as high drive inputs to a quadrant. Both as an I/O
control or high drive, these buffers can be driven by
the internal logic. The performance is indicated in
Table 6.
TABLE 6. I/O Control Network/Local High-Drive
Programmable Logic Routing
Six types of routing resources are provided, as in the
QuickRAM devices: short (sometimes called seg-
mented) wires, dual wires, quad wires, express wires,
distributed networks and defaults. Short wires span
the length of 1 logic cell, always in the vertical direc-
tion. Dual wires run horizontally and span the length
of 2 logic cells. Short and dual wires are predomi-
nantly used for local connections. They effectively
traverse one or two logic cells utilize an interconnect
element to continue to the next cell or to change
direction.
Quad
wires have passive link interconnect elements
every fourth logic cell. As a result, these wires are
typically used to implement intermediate length or
medium fan-out nets.
Express
lines run the length of the programmable
logic uninterrupted. Each of these lines has a higher
capacitance than a quad, dual or short wire, but less
capacitance than shorter wires connected to run the
length of the device. The resistance will also be lower
because the express wires don
’
t require the use of
"pass" links. Express wires provide higher perfor-
mance for long routes or high fan-out nets.
Distributed
networks are described in the clock/
control section. These wires span the programmable
logic, and are driven by "column clock" buffers. Each
dedicated clock network pin buffer is hard wired to a
set of column clock buffers. Five global networks
"global buffers" can be connected through special
purpose routing called "HSCK lines" to either a dedi-
cated pin buffer, or any vertical routing wire crossing
it.
Global POR (power-on reset)
The Eclipse family of devices features a global power-
on reset. This reset will be hardwired to all registers
and will reset the registers upon power-up of the
device. The circuitry used to support the global POR
is similar to the power-up loading circuitry.
FIGURE 12. Power-On Reset
Separate Power and Logic-cell Power
To decrease the logic cell area and to eliminate the
need for disable transistors in the input stage of the
logic cell, a separate power supply for the logic cells
has been added to the family. This supply will be
grounded during programming and for various test
modes.
TT, 25C, 2.5V
I/O (slow)
I/O (fast)
Skew
From Pad
1.00ns
0.63ns
0.37ns
From Array
1.14ns
0.78ns
0.36ns
P
ROGRAMMABLE
L
OGIC
R
OUTING
G
LOBAL
POR (
POWER
-
ON
RESET
)
VCC
Power-on
Reset
Q
XXXXXXX
0
S
EPARATE
P
OWER
AND
LOGIC
-
CELL
POWER
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