- 您现在的位置：买卖IC网 > PDF目录361292 > QL6250 (QuickLogic Corp.) Eclipse Family Combining Performance, Density, and Embedded RAM(Eclipse 系列性能、密度和嵌入式相结合的RAM) PDF资料下载
参数资料
| 型号： | QL6250 |
| 厂商： | QuickLogic Corp. |
| 英文描述： | Eclipse Family Combining Performance, Density, and Embedded RAM(Eclipse 系列性能、密度和嵌入式相结合的RAM) |
| 中文描述： | Eclipse的家庭结合性能，密度，和嵌入式内存（Eclipse的系列性能，密度和嵌入式相结合的内存） |
| 文件页数： | 7/12页 |
| 文件大小： | 258K |
| 代理商： | QL6250 |
5-7
Preliminary
Eclipse
TABLE 3. I/O Standards and Applications
As designs become more complex and requirements
more stringent, varying I/O standards are developing
for specific applications. I/O standards for proces-
sors, memories and various bus applications have
become common place and a requirement for many
systems. In addition, I/O timing has become a
greater issue with specific requirements for setup,
hold, clock to out, and switching times.
The Eclipse family has addressed these changing sys-
tem requirements. The Eclipse family includes a com-
pletely new I/O cell which consists of programmable
I/Os as well as a new cell structure consisting of 3
registers - input, output and output enable. Eclipse
will offer banks of programmable I/O that addresses
many of the new bus standards that are popular
today. In addition, the input register addresses the
setup time; the output register addresses clock-to-out
time; and the OE register addresses the switching
time from high impedance to a given value.
FIGURE 7. Eclipse I/O Cell
The bi-directional I/O pin options can be pro-
grammed for input, output, or bi-directional opera-
tion. As shown in Figure 7, each bi-directional I/O
pin is associated with an I/O cell which features an
input/feedback register, an input buffer, output/feed-
back register, three-state output buffer, an output
enable register, and two (2) two-to-one multiplexers.
For input functions, I/O pins can provide combinato-
rial, registered data or both options simultaneously to
the logic array. For combinatorial input operation,
data is routed from I/O pins through the input buffer
to the array logic. For registered input operation, I/
O pins drive the D input of input cell registers, allow-
ing data to be captured with fast set-up times without
consuming internal logic cell resources.
For output functions, I/O pins can receive combina-
torial or registered data from the logic array. For
combinatorial output operation, data is routed from
the logic array through a multiplexer to the I/O pin.
For registered output operation, the array logic drives
the D input of the output cell register which in turn
drives the I/O pin through a multiplexer. The multi-
plexer allows either a combinatorial or a registered
signal to be driven to the I/O pin.
The three-state output buffer controls the flow of data
from the array logic to the I/O pin and allows the I/O
pin to act as an input and/or output. The buffer
’
s
output enable can be individually controlled by a logic
cell array or any pin (through the regular routing
resources), or bank-controlled through one of the glo-
bal networks. The signal can be also be either combi-
natorial or registered. This is identical to that of the
flow for the output cell. For combinatorial control
operation data is routed from the logic array through
a multiplexer to the three-state control. For regis-
tered control operation, the array logic drives the D
input of the OE cell register which in turn drives the
three-state control through a multiplexer. The multi-
plexer allows either a combinatorial or a registered
signal to be driven to the three-state control. For out-
put functions, I/O pins can be individually configured
for active HIGH, active LOW, or open-drain inverting
operation. In the active HIGH and active LOW
modes, the pins of all devices are fully 3.3V compli-
ant.
When I/O pins are unused, the OE controls can be
permanently disabled, allowing the output cell regis-
ter to be used for registered feedback into the logic
array. I/O cell registers are controlled by clock, clock
enable, and reset signals, which can come from the
regular routing resources, from one of the global net-
works, or from two input pins per bank of I/O
’
s. The
CLK and RESET signals share a common line, while
the clock enables for each register can be indepen-
dently controlled. Additionally the output and enable
相关PDF资料 |
PDF描述 |
|---|---|
| QL6600 | Eclipse Family Combining Performance, Density, and Embedded RAM(Eclipse 系列性能、密度和嵌入式相结合的RAM) |
| QL6325 | Eclipse Family Combining Performance, Density, and Embedded RAM(Eclipse 系列性能、密度和嵌入式相结合的RAM) |
| QL6500 | Eclipse Family Combining Performance, Density, and Embedded RAM(Eclipse 系列性能、密度和嵌入式相结合的RAM) |
| QL63D5SA | InGaAlP Laser Diode |
| QL63F5SA | InGaAlP Laser Diode |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL62506PB516C | 制造商:QUICK LOG 功能描述:New |
| QL6325PQ208 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| QL6325PT280 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| QL63D5SA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:InGaAlP Laser Diode |
| QL63F5SA | 制造商:未知厂家 制造商全称:未知厂家 功能描述:InGaAlP Laser Diode |
发布紧急采购，3分钟左右您将得到回复。