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参数资料
| 型号： | QL6250 |
| 厂商： | QuickLogic Corp. |
| 英文描述： | Eclipse Family Combining Performance, Density, and Embedded RAM(Eclipse 系列性能、密度和嵌入式相结合的RAM) |
| 中文描述： | Eclipse的家庭结合性能，密度，和嵌入式内存（Eclipse的系列性能，密度和嵌入式相结合的内存） |
| 文件页数： | 6/12页 |
| 文件大小： | 258K |
| 代理商： | QL6250 |
5-6
Preliminary
Eclipse
FIGURE 6. PLL Block Diagram
PLL Features
I
Phase and frequency lock
Lock range: 25 MHz to 250 MHz
Jitter: < 200 ps across all ranges
Lock time: <200 steps or <10 us (which ever is less)
Early clock option for Tco <= 3 ns
No external components
Frequency multiply and divide @ 4X, 2X, 1X, 0.5X
input frequency
Lock detect for system start-up
Phased locked output option @ 4X, 2X, 1X, 0.5X input
frequency
PLL standby/bypass mode
I
I
I
I
I
I
I
I
I
I/O Cell Structure
Eclipse features a variety of distinct I/O pins to
maximize performance, functionality, and flexibility
with bi-directional I/O pins and input-only pins. All
input and I/O pins are 2.5V and 3.3V tolerant and
comply with the specific I/O standard selected. The
outputs swing from Vss to VCCI/O (0V to 3.3V ±
10%). The VCCI/O pins must be tied to a 3.3V
supply to provide 3.3V compliance. If 3.3V
compliance is not required, then these pins must be
tied to the 2.5V supply. Eclipse can also support
LVDS and LVPECL I/O standards with the addition
of an external resistor. Table 3 summarizes the I/O
specifications that will be supported.
Filter
VCO
buf
buf
buf
Early clock
delay
ClockTree
Frequency
divide
Frequency
multiply
÷ 1
VCO Frequency
range adjust and
PLL bypass
Fin
Fout
Match Fout
≈
clock tree
÷ 1
÷ 2
÷ 1
÷ 2
+
Lock detect
Loop filter
adjust
Delay
PLL
Reset
Phase detector
÷ 2
÷ 4
PLL F
EATURES
I/O C
ELL
S
TRUCTURE
I/O Standard Reference Voltage
LVTTL
LVCMOS2
PCI
GTL+
SSTL3
SSTL2
Output Voltage
3.3
2.5
3.3
n/a
3.3
2.5
Application
general purpose
general purpose
PCI bus applications
high speed bus - Pentium Pro
memory bus - Hitachi, IBM
memory bus - Hitachi, IBM
n/a
n/a
n/a
1
1.5
1.25
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