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参数资料
| 型号： | QL6250 |
| 厂商： | QuickLogic Corp. |
| 英文描述： | Eclipse Family Combining Performance, Density, and Embedded RAM(Eclipse 系列性能、密度和嵌入式相结合的RAM) |
| 中文描述： | Eclipse的家庭结合性能，密度，和嵌入式内存（Eclipse的系列性能，密度和嵌入式相结合的内存） |
| 文件页数： | 4/12页 |
| 文件大小： | 258K |
| 代理商： | QL6250 |
5-4
Preliminary
Eclipse
RAM Modules
The Eclipse Family includes multiple dual-port 2,304-
bit RAM modules for implementing RAM, ROM and
FIFO functions. Each module is user-configurable
into four different block organizations. Modules can
also be cascaded horizontally to increase their effec-
tive width or vertically to increase their effective
depth as shown in Figure 3. The RAM can also be
configured as a modified Harvard Architecture, simi-
lar to those found in DSPs.
FIGURE 3. 2,304-bit QuickRAM Module
The number of RAM modules varies from 12 to 36
blocks within the Eclipse family, for a total of 46.1K
to 82.9k bits of RAM. Using two "mode" pins,
designers can configure each module into 128 x 18
(Mode 0), 256 x 9 (Mode 1), 512 x 4 (Mode 2), or
1024 x 2 blocks (Mode 3). The blocks are also easily
cascadable to increase their effective width and/or
depth. See figure 4.
FIGURE 4. Cascaded RAM Modules
The RAM modules are dual-port, with completely
independent READ and WRITE ports and separate
READ and WRITE clocks. The READ ports support
asynchronous and synchronous operation, while the
WRITE ports support synchronous operation. Each
port has 18 data lines and 10 address lines, allowing
word lengths of up to 18 bits and address spaces of
up to 1024 words. Depending on the mode
selected, however, some higher order data or address
lines may not be used.
The Write Enable (WE) line acts as a clock enable for
synchronous write operation. The Read Enable (RE)
acts as a clock enable for synchronous READ opera-
tion (ASYNCRD input low), or as a flow-through
enable for asynchronous READ operation (ASYN-
CRD input high).
Designers can cascade multiple RAM modules to
increase the depth or width allowed in single modules
by connecting corresponding address lines together
and dividing the words between modules.
A similar technique can be used to create depths
greater than 512 words. In this case address signals
higher than the ninth bit are encoded onto the write
enable (WE) input for WRITE operations. The READ
data outputs are multiplexed together using encoded
higher READ address bits for the multiplexer
SELECT signals.
The RAM blocks can be loaded with data generated
internally (typically for RAM or FIFO functions) or
with data from an external PROM (typically for ROM
functions). The RAM achieve 155 MHz perfor-
mance for the lowest speed grade devices when using
multiple blocks cascaded together.
RAM M
ODULES
MODE[1:0]
WA[9:0]
WD[17:0]
WE
WCLK
2,304-bit Module
ASYNCRD
RA[9:0]
RD[17:0]
RE
RCLK
WDATA
RDATA
RDATA
WADDR
WDATA
RADDR
RAM
Module
(2,304 bits)
RAM
Module
(2,304 bits)
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