2
Preliminary
5-2
Eclipse
TABLE 1. Eclipse Product Family Members
Quick
Works
Design Software
The turnkey QuickWorks package provides the most
complete ESP and FPGA software solution from
design entry to logic synthesis, to place and route to
simulation. The packages provide a solution for
designers who use third party tools from Cadence,
Mentor, OrCAD, Synopsys, Viewlogic, Veribest and
other third-party tools for design entry, synthesis, or
simulation.
Process Data
Eclipse is fabricated on a .25u 5 layer metal CMOS
process. The core voltage is 2.5 volt Vcc supply and
3.3 tolerant I/O with the addition of 3.3 volt Vccio.
Eclipse is available in commercial, industrial, and mili-
tary temperature grades.
Programmable Logic Architectural Overview
The Eclipse features an enhanced Supercell with an
additional D flip-flop register and associated control
logic. This advanced architectural approach,
addresses today’s highly register intensive designs.
QL6250
248,160
40x24
960
2,688
256
20
46,100
208
516
484
280
QL6325
320,640
48x32
1,536
4,302
320
24
55,300
208
516
484
280
QL6500
488,064
64x48
3,072
7,488
448
32
73,700
QL6600
583,008
72x56
4,032
9,600
512
36
82,900
Max Gates
Logic Array
Logic Cells
Max Flip-Flops
Max I/O
RAM Modules
RAM bits
Packages
PQFP
BGA (1.27mm)
BGA (1.0mm)
FPBGA (0.8mm)
516
516
484, 672
280
484, 672
280
D
ESIGN
S
OFTWARE
Q
UICK
W
ORKS
P
ROCESS
D
ATA
P
ROGRAMMABLE
L
OGIC
A
RCHITECTURAL
O
VERVIEW