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参数资料
| 型号： | QL6500 |
| 厂商： | QuickLogic Corp. |
| 英文描述： | Eclipse Family Combining Performance, Density, and Embedded RAM(Eclipse 系列性能、密度和嵌入式相结合的RAM) |
| 中文描述： | Eclipse的家庭结合性能，密度，和嵌入式内存（Eclipse的系列性能，密度和嵌入式相结合的内存） |
| 文件页数： | 5/12页 |
| 文件大小： | 258K |
| 代理商： | QL6500 |
5-5
Preliminary
Eclipse
Multiple Accessing of Memories
The extremely fast RAM can be used in designs that
require multiple memory accessing. The RAM
achieves 280 MHz performance for the fastest speed
grade and 155 MHz performance for the lowest
speed grade devices when using multiple blocks cas-
caded together. Write through of DATA is also possi-
ble with the QuickLogic RAM.
PLL
Phase Lock Loops (PLLs), also known as frequency
synthesizers, are used to create a master clock from a
lower input frequency clock in DSPs. There are four
PLLs in the Eclipse family, one is multiplexed with
the dedicated clock and the remaining three connect
to global clocks. The PLLs have a frequency range of
25MHz to 250MHz. Frequency synthesis can also
be created in increments of multiply by 2, 4 and
divide by 2, 4. In addition, there is an early clock
option to further reduce the TCO of a system and a
PLL output option to drive external devices. A lock
detect signal is provided to indicate a PLL is in lock.
FIGURE 5. PLL Clock Network
M
ULTIPLE
A
CCESSING
OF
M
EMORIES
PLL
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