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参数资料
| 型号： | QL6500 |
| 厂商： | QuickLogic Corp. |
| 英文描述： | Eclipse Family Combining Performance, Density, and Embedded RAM(Eclipse 系列性能、密度和嵌入式相结合的RAM) |
| 中文描述： | Eclipse的家庭结合性能，密度，和嵌入式内存（Eclipse的系列性能，密度和嵌入式相结合的内存） |
| 文件页数： | 9/12页 |
| 文件大小： | 258K |
| 代理商： | QL6500 |
5-9
Preliminary
Eclipse
Clock Networks
Global Clocks
There are 8 global clock networks in the Eclipse
device family. Global clocks can drive logic cell, I/O,
and RAM registers in the device. Three Global clocks
will each have access to a PLL. Five global clocks will
have access to a Quad Net (local clock network) con-
nection with a programmable connection to the reg-
ister inputs.
FIGURE 10. Global Clock Methodology
Quad-Net NETWORK
There are 5 Quad-Net local clock networks in each
quadrant for a total of 20 in a device. Each Quad-Net
is local to a quadrant. Quad-Net is multiplexed with
the clock buffer before driving the column clock
buffers.
Dedicated Clock
There is one dedicated clock in the Eclipse device
family. It connects to the clock input of the
SuperCell, I/O and RAM registers through a
hardwired connection and is multiplexed with the
programmable clock input. There are four
inversions from pad to register inputs and the
dedicated clock takes on the same configuration as
the global clock. The dedicated clock provides a fast
global network with low skew. The dedicated clock
has access to one of four PLL
’
s. You have the ability
to select either the dedicated clock or the
programmable clock, Figure 11. The performance of
the dedicated clock is given in Table 5.
FIGURE 11. Dedicated clock circuitry within
logic cell
TABLE 5. Dedicated Clock Performance
C
LOCK
N
ETWORKS
Clock Performance
Global
1.51 ns
2.06 ns
0.55 ns
TT, 25C, 2.5V
Macro (near)
I/O (far)
Skew
Dedicated
1.59 ns
1.73 ns
0.14 ns
CLK
Programmable clock
Hard-wired clock
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