5-3
Preliminary
Eclipse
TABLE 2. Performance Standards
The Eclipse logic Supercell structure, Figure 2, is sim-
ilar to the .35 mm QuickLogic logic cell with the
addition of a second register. Both registers share
CLK, SET and RESET inputs. The second register
has a two-to-one multiplexer controlling its input.
The register can be loaded from the NZ output or
directly from a dedicated input. NOTE: The input
"PP" is not an "input" in the classical sense. It can
only be tied high or low using default links only and is
used to select which path "NZ" or "PS" is used as an
input to the register. All other inputs can be con-
nected not only to "tiehi" and "tielo" but to multiple
routing channels as well.
The complete logic cell consists of two 6-input AND
gates, four two-input AND gates, seven two-to-one
multiplexers and two D flip-flop with asynchronous
SET and RESET controls. The cell has a fan-in of 30
(including register control lines) and fits a wide range
of functions with up to 17 simultaneous inputs. It has
6 outputs, 4 combinatorial and 2 registered. The
high logic capacity and fan-in of the logic cell accom-
modate many user functions with a single level of
logic delay while other architectures require two or
more levels of delay
FIGURE 2. Eclipse SuperCell
Function
Description
Slowest
speed grade
5 ns
6 ns
6 ns
250 MHz
250 MHz
155 MHz
155 MHz
155 MHz
4.5 ns
200 MHz
Fastest
speed grade
2.8 ns
3.4 ns
3.4 ns
450 MHz
450 MHz
280 MHz
280 MHz
280 MHz
2.5 ns
400 MHz
Multiplexer
Parity Tree
16:1
24
36
16 bit
32 bit
128 x 32
256 x 16
128 x 64
Counter
FIFO
Clock to out
System
clock
QS
A1
A2
A3
A4
A5
A6
OS
OP
B1
B2
C1
C2
MP
MS
D1
D2
E1
E2
NP
NS
F1
F2
F3
F4
F5
F6
PS
PP
QR
AZ
OZ
QZ
NZ
FZ
Q2Z