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参数资料
| 型号： | R1EX25512ATA00A#S0 |
| 厂商： | Renesas Electronics America |
| 文件页数： | 18/22页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 512K 5MHZ 8TSSOP |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 512K (64K x 8) |
| 速度： | 3MHz，5MHz |
| 接口： | SPI 串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 标准包装 |
| 其它名称： | R1EX25512ATA00A#S0DKR |
R1EX25512ASA00A/R1EX25512ATA00A
Hold Condition
The hold ( HOLD ) signal is used to pause any serial communications with the device without resetting the clocking
sequence.During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial
clock (C) are don’t care.To enter the hold condition, the device must be selected, with chip select ( S ) low.
Normally, the device is kept selected, for the whole duration of the hold condition. Deselecting the device while it is in
the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to
reset any processes that had been in progress.
The hold condition starts when the hold ( HOLD ) signal is driven low at the same time as serial clock (C) already being
low (as shown in the following figure).The hold condition ends when the hold ( HOLD ) signal is driven high at the same
time as serial clock (C) already being low.
The following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock
(C) being low.
Hold Condition Activation
HOLD status
HOLD status
C
HOLD
Notes
Data Protection at V CC On/Off
When V CC is turned on or off, noise on S inputs generated by external circuits (CPU, etc) may act as a trigger and turn
the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM have a power
on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly.
? S should be fixed to V CC during V CC on/off. Low to high or high to low transition during V CC on/off may
cause the trigger for the unintentional programming.
? V CC should be turned on/off after the EEPROM is placed in a standby state.
? V CC should be turned on from the ground level (V SS ) in order for the EEPROM not to enter the unintentional
programming mode.
? V CC turn on rate should be slower than 2 μ s/V.
? When WRSR or WRITE instruction is executed before V CC turns off, V CC should be turned off after waiting
write cycle time (t W ).
? When setting the chip select signal ( S) to the low level at power on, wait for 10 ms or longer after the supply
voltage 1.8V.
1.8V
(Vccmin)
Vcc
S
10ms min
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Page 18 of 20
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相关代理商/技术参数 |
参数描述 |
|---|---|
| R1EX25512ATA00I | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Serial Peripheral Interface 512K EEPROM (64-Kword × 8-bit) |
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