参数资料
型号: R5F21272SNFP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP32
封装: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件页数: 34/52页
文件大小: 620K
代理商: R5F21272SNFP
57
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
13. External interrupts
The External Interrupts are triggered by the INT0 pin or any of the PCINT30:0 pins
(2). Observe that, if enabled, the
interrupts will trigger even if the INT0 or PCINT30:0 pins are configured as outputs. This feature provides a way of
generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15:8 pin toggles.
Pin change interrupts PCI0 will trigger if any enabled PCINT7:0 pin toggles. The PCMSK3
(1), PCMSK2 (1),
PCMSK1, and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change interrupts
on PCINT30:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also
from sleep modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the
specification for the ”EICRA – External Interrupt Control Register A” on page 58. When the INT0 interrupt is
enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. . Note that rec-
ognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, described in ”Clock
systems and their distribution” on page 27. Low level interrupt on INT0 is detected asynchronously. This implies
that this interrupt can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is
halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long
enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of
the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in ”System clock and clock options” on page 27.
Notes:
1. PCMSK3 and PCMSK2 are only present in Atmel ATmega3250A/3250PA/6450A/6450P.
2. PCINT30:16 are only present in ATmega3250A/3250PA/6450A/6450P. Only PCINT15:0 are present in Atmel
ATmega165A/165PA; ATmega325A/325PA and ATmega645A/645P. See ”Pin configurations” on page 2 and ”Reg-
13.1
Pin change interrupt timing
An example of timing of a pin change interrupt is shown in Figure 13-1 on page 57.
Figure 13-1. Pin change interrupt.
clk
PCINT(n)
pin_lat
pin_sync
pcint_in_(n)
pcint_syn
pcint_setflag
PCIF
PCINT(0)
pin_sync
pcint_syn
pin_lat
D
Q
LE
pcint_setflag
PCIF
clk
PCINT(0) in PCMSK(x)
pcint_in_(0)
0
x
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