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参数资料
型号： R5F56217BDLE#U0
厂商： Renesas Electronics America
文件页数： 99/148页
文件大小： 0K
描述： MCU 32BIT FLASH 384KROM 145TFLGA
产品培训模块： RX Compare Match Timer
RX DMAC
标准包装： 1
系列： RX600
核心处理器： RX
芯体尺寸： 32-位
速度： 100MHz
连通性： CAN，EBI/EMI，I²C，SCI，SPI，USB
外围设备： DMA，LVD，POR，PWM，WDT
输入/输出数： 103
程序存储器容量： 384KB（384K x 8）
程序存储器类型： 闪存
RAM 容量： 64K x 8
电压 - 电源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
数据转换器： A/D 8x10/12b，D/A 2x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 145-TFLGA
包装： 托盘
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 52
2004 Microchip Technology Inc.
TABLE 4-3:
REGISTER FILE SUMMARY
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
TOSU
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
32, 42
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
32, 42
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
32, 42
STKPTR
STKFUL
STKUNF
—
Return Stack Pointer
00-0 0000
32, 43
PCLATU
—
bit 21
Holding Register for PC<20:16>
--10 0000
32, 44
PCLATH
Holding Register for PC<15:8>
0000 0000
32, 44
PCL
PC Low Byte (PC<7:0>)
0000 0000
32, 44
TBLPTRU
—
—bit 21(2)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
32, 64
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
32, 64
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
32, 64
TABLAT
Program Memory Table Latch
0000 0000
32, 64
PRODH
Product Register High Byte
xxxx xxxx
32, 85
PRODL
Product Register Low Byte
xxxx xxxx
32, 85
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
32, 89
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
1111 1111
32, 90
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
1100 0000
32, 91
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
n/a
57
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented
(not a physical register)
n/a
57
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented
(not a physical register)
n/a
57
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
n/a
57
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented
(not a physical register) – value of FSR0 offset by value in WREG
n/a
57
FSR0H
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000
32, 57
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
32, 57
WREG
Working Register
xxxx xxxx
32
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
n/a
57
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented
(not a physical register)
n/a
57
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented
(not a physical register)
n/a
57
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented
(not a physical register)
n/a
57
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented
(not a physical register) – value of FSR1 offset by value in WREG
n/a
57
FSR1H
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000
33, 57
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx
33, 57
BSR
—
Bank Select Register
---- 0000
33, 56
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
n/a
57
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented
(not a physical register)
n/a
57
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented
(not a physical register)
n/a
57
Legend:
x
= unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
2:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
3:
These registers are unused on PIC18F6X20 devices; always maintain these clear.
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