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参数资料
| 型号： | R5F64601KFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 36/75页 |
| 文件大小： | 663K |
| 代理商： | R5F64601KFP |
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60
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in
SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
This flag is always cleared when INT0 is configured as a level interrupt.
13.2.4
PCMSK3 – Pin Change Mask Register 3 (1)
Note:
1. PCMSK3 and PCMSK2 are only present in Atmel ATmega3250A/3250PA/6450A/6450P.
Bit 6:0 – PCINT30:24: Pin Change Enable Mask 30:24
Each PCINT30:24-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT30:24
is set and the PCIE3 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If
PCINT30:24 is cleared, pin change interrupt on the corresponding I/O pin is disabled.
13.2.5
PCMSK2 – Pin Change Mask Register 2 (1)
Note:
1. PCMSK3 and PCMSK2 are only present in ATmega3250A/3250PA/6450A/6450P.
Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16
Each PCINT23:16 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16
is set and the PCIE2 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If
PCINT23:16 is cleared, pin change interrupt on the corresponding I/O pin is disabled.
13.2.6
PCMSK1 – Pin Change Mask Register 1
Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is
set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8
is cleared, pin change interrupt on the corresponding I/O pin is disabled.
13.2.7
PCMSK0 – Pin Change Mask Register 0
Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0
Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set
and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is
cleared, pin change interrupt on the corresponding I/O pin is disabled.
Bit
7
65432
10
(0x73)
–
PCINT30
PCINT29
PCINT28
PCINT27
PCINT26
PCINT25
PCINT24
PCMSK3
Read/Write
R
R/W
Initial Value
0
00000
00
Bit
7
654
321
0
(0x6D)
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
PCMSK2
Read/Write
R/W
Initial Value
0
Bit
7
6
5432
1
0
(0x6C)
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
PCMSK1
Read/Write
R/W
Initial Value
0
0000
0
Bit
7
654
32
10
(0x6B)
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
PCMSK0
Read/Write
R/W
Initial Value
0
000
00
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