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参数资料
| 型号： | R5F64601KFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 73/75页 |
| 文件大小： | 663K |
| 代理商： | R5F64601KFP |
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94
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Bit 5:4 – COM0A1:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the
OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data
Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting.
Table 15-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-
PWM).
Table 15-4 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is ignored,
but the set or clear is done at BOTTOM. See ”Fast PWM mode” on page 89 for more details.
Table 15-5 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is ignored,
but the set or clear is done at TOP. See ”Phase Correct PWM mode” on page 90 for more details.
Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 15-3.
Compare Output mode, non-PWM mode.
COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
0
1
Toggle OC0A on compare match
1
0
Clear OC0A on compare match
1
Set OC0A on compare match
Table 15-4.
Compare Output mode, fast PWM mode
COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
01
Reserved
10
Clear OC0A on compare match, set OC0A at BOTTOM
(non-inverting mode)
11
Set OC0A on compare match, clear OC0A at BOTTOM
(inverting mode)
Table 15-5.
Compare Output mode, phase correct PWM mode
(1).
COM0A1
COM0A0
Description
0
Normal port operation, OC0A disconnected.
01
Reserved
10
Clear OC0A on compare match when up-counting. Set OC0A on
compare match when down counting.
11
Set OC0A on compare match when up-counting. Clear OC0A on
compare match when down counting.
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