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参数资料
| 型号： | R5F71474BJ80FPV |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件页数： | 8/123页 |
| 文件大小： | 6757K |
| 代理商： | R5F71474BJ80FPV |
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173
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Bit 4 – FEn: Frame Error n
This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop
bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The
FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA.
Bit 3 – DORn: Data OverRun n
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two
characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is
valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.
Bit 2 – UPEn: USART Parity Error n
This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking
was enabled at that point (UPM1n = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to
zero when writing to UCSRnA.
Bit 1 – U2Xn: Double the USART Transmission Speed n
This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer
rate for asynchronous communication.
Bit 0 – MPCMn: Multi-processor Communication Mode n
This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to one, all the incoming
frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is
unaffected by the MPCMn setting. For more detailed information see ”Multi-processor Communication Mode” on
20.11.3
UCSRnB – USART Control and Status Register n B
Bit 7 – RXCIEn: RX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete interrupt will be generated
only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXC bit in UCS-
RnA is set.
Bit 6 – TXCIEn: TX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated
only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCS-
RnA is set.
Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only
if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCS-
RnA is set.
Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxD
pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn
Flags.
Bit
7654
321
0
(0xC1)
RXCIEn
TXCIEn
UDRIEn
RXENn
TXENn
UCSZn2
RXB8n
TXB8n
UCSRnB
Read/Write
R/W
RR/W
Initial Value
0000
000
0
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