26
Datasheet
Pentium III Processor for the PGA370 Socket at 500 MHz to 1 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All specifications in this table apply only to the Pentium III processor. For motherboard compatibility with the
Intel CeleronTM processor, see the
Intel CeleronTM Processor Datasheet.
3. VccCORE and IccCORE supply the processor core and the on-die L2 cache.
4. Use the “typical voltage” specification with the “tolerance specifications” to provide correct voltage regulation
to the processor.
5. VTT and Vcc1.5 must be held to 1.5V ±9% while the AGTL+ bus is active. It is required that VTT and Vcc1.5 be
held to 1.5V ±3% while the processor system bus is static (idle condition). The ±3% range is the required
design target; ±9% will come from the transient noise added. This is measured at the PGA370 socket pins on
the bottom side of the baseboard.
6. These are the tolerance requirements, across a 20 MHz frequency bandwidth, measured at the
processor socket pin on the soldered-side of the motherboard. VCCCORE must return to within the static
voltage specification within 100
s after a transient event; see the VRM 8.4 DC-DC Converter Design
Guidelines for further details.
7. VREF should be generated from VTT by a voltage divider of 1% resistors or 1% matched resistors. Refer to the
Intel
Pentium II Processor Developer’s Manual for more details on VREF.
8. Maximum ICC is measured at VCC typical voltage and under a maximum signal loading conditions.
9. Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of VccCORE
(VccCORE_TYP). In this case, the maximum current level for the regulator, IccCORE_REG, can be reduced from
the specified maximum current IccCORE _MAX and is calculated by the equation:
IccCORE_REG = IccCORE_MAX × (VccCORE_TYP - VccCORE_STATIC_TOLERANCE) / VccCORE_TYP
10.The current specified is the current required for a single processor. A similar amount of current is drawn
through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is
used (see Section 2.1).
11. The current specified is also for AutoHALT state.
12.Maximum values are specified by design/characterization at nominal VccCORE.
13.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
14.dIcc/dt specifications are measured and specified at the PGA370 socket pins.
15.CLKREF must be held to 1.25V ±6.5%. This tolerance accounts for a ±5% power supply and ±1% resistor
divider tolerance. It is recommended that the motherboard generate the CLKREF reference from either the
2.5V or 3.3V supply. VTT should not be used due to risk of AGTL+ switching noise coupling to this analog
reference.
16.Static voltage regulation includes: DC output initial voltage set point adjust, Output ripple and noise, Output
load ranges specified in the tables above.
17.FMB - Flexible Motherboard recommendation
18.These values are estimates based on preliminary simulation.
ICLKREF
CLKREF voltage
supply current
60
A
IVTT
Termination voltage
supply current
2.7
A
10
ISGnt
ICC Stop-Grant for
processor core
2.5
A
8, 11
ISLP
ICC Sleep for processor
core
2.5
A
8
IDSLP
ICC Deep Sleep for
processor core
2.2
A
dICC
CORE/dt
Power supply current
slew rate
240
A/s
12, 13, 14
dIvTT/dt
Termination current
slew rate
8A/s
12, 13, See
Table 9
Table 6.
Voltage and Current Specifications 1, 2 (Sheet 3 of 3)
Symbol
Parameter
Processor
Min
Typ
Max
Unit
Notes
Core
Freq
CPUID