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参数资料
| 型号： | RB80526PY500256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 500 MHz, MICROPROCESSOR, CPGA370 |
| 封装： | FCPGA-370 |
| 文件页数： | 69/80页 |
| 文件大小： | 569K |
| 代理商： | RB80526PY500256 |
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Datasheet
71
Pentium III Processor for the PGA370 Socket at 500 MHz to 1 GHz
7.0
Processor Signal Description
This section provides an alphabetical listing of all the Intel Pentium III processor signals. The
tables at the end of this section summarize the signals by direction: output, input, and I/O.
7.1
Alphabetical Signals Reference
Table 33. Signal Description (Sheet 1 of 8)
Name
Type
Description
A[35:3]#
I/O
The A[35:3]# (Address) signals define a 236-byte physical memory address space.
When ADS# is active, these pins transmit the address of a transaction; when ADS#
is inactive, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the processor system bus. The
A[35:24]# signals are parity-protected by the AP1# parity signal, and the A[23:3]#
signals are parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[35:3]#
pins to determine their power-on configuration. See the Intel
Pentium II
Processor Developer’s Manual for details.
A20M#
I
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M# emulates the
8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M#
is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
ADS#
I/O
The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[35:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all processor system bus agents.
AERR#
I/O
The AERR# (Address Parity Error) signal is observed and driven by all processor
system bus agents, and if used, must connect the appropriate pins on all processor
system bus agents. AERR# observation is optionally enabled during power-on
configuration; if enabled, a valid assertion of AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent
may handle an assertion of AERR# as appropriate to the error handling architecture
of the system.
AP[1:0]#
I/O
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with
ADS#, A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and AP0# covers
A[23:3]#. A correct parity signal is high if an even number of covered signals are low
and low if an odd number of covered signals are low. This allows parity to be high
when all the covered signals are high. AP[1:0]# should connect the appropriate pins
of all processor system bus agents.
BCLK
I
The BCLK (Bus Clock) signal determines the bus frequency. All processor system
bus agents must receive this signal to drive their outputs and latch their inputs on
the BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RB80526PY600256 | 制造商:Intel 功能描述:MPU Pentium 制造商:Rochester Electronics LLC 功能描述:PENTIUM-III 0.18 MICRON 600MHZ 3.3V 370-PIN FCPGA - Bulk |
| RB80526PY600256S L5BT | 功能描述:IC PENTIUM III 600MHZ FC-PGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| RB80526PY600256SL5BT | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 64-Bit 0.18um 600MHz 370-Pin FCPGA |
| RB80526PY700256 | 制造商:Intel 功能描述:MPU Pentium? III Processor 64-Bit 0.18um 700MHz 370-Pin FCPGA 制造商:Rochester Electronics LLC 功能描述:PIII 700/100 256K ON DIE FC-PGA - Bulk |
| RB80526PY700256S L4ZM | 功能描述:IC PENTIUM III 700MHZ FC-PGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
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