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参数资料
| 型号： | RC7144 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 10/16页 |
| 文件大小： | 61K |
| 代理商： | RC7144 |
PRODUCT SPECIFICATION
RC7144
3
Pr
eliminar
y
Infor
mation
Pin Description
Pin Name
Pin #
Pin Type
Pin Function
VDDQ3
1, 6, 14, 19,
27, 30, 36
PWR
Power connection: Power supply for core logic, PLL circuitry SDRAM
outputs, PCI outputs, reference, 48 & 24 MHz outputs. Connect to 3.3
Volts.
REF0/
PCI_STOP#
2
OUT/IN
I/O Dual function REF0 & PCI_STOP#: Function determined by
MODE pin. When high, this pin is an output with 14.31818 MHz of
reference clock. When MODE is low, PCI_STOP# stops all the PCI
clocks.
GND
3, 9, 16, 22,
33, 39, 45
PWR
Ground connection: Connect all ground pins to the common system
ground plane.
X1
4
IN
Crystal Connection: An input connection for an external 14.318 MHz
crystal. 18 pF internal cap.
X2
5
OUT
Crystal Connection or External Reference Frequency: This pin has
dual functions. It can be used as an external 14.318 MHz crystal
connection or as an external reference frequency input.
PCI_F/MODE
7
OUT/IN
Fixed PCI clock output: Upon power up MODE input will be latched,
which will enable or disable REF0.
PCI1/FS3
8
OUT/IN
PCI clock output: Upon power up FS3 input will be latched, which will
set clock frequencies as frequency selection table. This pin has internal
pull down.
PCI2:5
10, 11, 12, 13
OUT
PCI clock output 2 through 5: These five PCI clock outputs are
controlled by the PCI_STOP# control pin.
SDRAM_IN
15
IN
Buffered input pin: The signal provided to this input pin is buffered to
13 outputs.
SDRAM0:11;
SDRAM_F
17, 18, 20, 21,
28, 29, 31, 32,
34, 35, 37, 38,
40
OUT
SDRAM Clock Ouputs: SDRAM0:11 clock are determined by
FS0: FS3. SDRAM_F is a free running clock which is not controlled
by the I2C.
SDA
23
IN/OUT
Data pin for I2C circuitry.
SCL
24
IN
Clock pin for I2C circuitry.
24MHz/FS1
25
OUT/IN
24 MHz clock output: 24 MHz is provided in normal operation. In
standard systems, this output can be used as the clock input for Super
I/O chip. Upon power up FS1 input will be latched, which will set clock
frequencies as frequency selection table.
48MHz/FS0
26
OUT/IN
48 MHz clock output: 48 MHz is provided in normal operation. In
standard systems, this output can be used as the reference for
universal Serial Bus. Upon power up FS0 input will be latched, which
will set clock frequencies as frequency selection table.
CLK_STOP#
41
IN
CLK_STOP# Input: When 0, this pin stops the CPU outputs after
completing a full clock cycle. This pin does not effect CPU_F.
VDDQ2
42, 48
PWR
Power supply for IOAPIC & all CPU outputs. Connect to 2.5 or 3.3
Volts.
CPU1,
CPU_F
43, 44
OUT
CPU output clocks: VDDQ2 controls output Voltage. Stopped when
CLK_STOP# is 0. CPU_F is not affected by CLK_STOP#.
REF1/FS2
46
OUT/IN
Reference Clock output: 14.31818 MHz reference output. Upon
power up FS2 input will be latched, which will set clock frequencies as
frequency selection table.
IOAPIC
47
OUT
IOAPIC clock: Provides 14.31818 MHz fixed clock. VDDQ2 contols the
output Voltage.
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