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参数资料
| 型号： | RC7144 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 12/16页 |
| 文件大小： | 61K |
| 代理商： | RC7144 |
PRODUCT SPECIFICATION
RC7144
5
Pr
eliminar
y
Infor
mation
Functional Description
I/O Pin Operation
Dual Purpose I/O pins such as pin 8 FS3/PCI1, act as a logic
input upon power up. This allows the determination of
assigned device function. For example, FS3 along with the
other three select pins will determine the clock frequencies
as shown in the table. A short time after power up, the logic
state is latched and the pin becomes a clock output pin. For
example, pin 8 becomes a PCI clock output. This feature
reduces device pin count by combining clock outputs with
input select pins.
An external 10k ohm “strapping” resistor is connected
between the I/O pin and VDD or VSS (ground). A connec-
tion to ground sets a “0” bit and a connection to VDD sets a
“1” bit. See Figure 1.
Upon power up, the rst 2mS of operation is used for input
logic selection. The clock output pins are tri-stated, allowing
the output strapping resistor on the I/O pin to pull the pin and
its associated capacitive clock load to either a logic high or
low state. At the end of the 2mS period, the established logic
“0” or “1” condition of the I/O pin is then latched. Next the
output buffer is enabled which converts the I/O pin into an
operating clock output. The 2mS timer is started when VDD
(3.3V) reaches 2.0V. The input bits can only be reset by turn-
ing the VDD off and then back on again.
It should be noted that the strapping resistors have no signi-
cant effect on clock output signal integrity. The drive imped-
ance of outputs is 20 ohms (nominal) which is minimally
affected by the 10kohm strap to ground or VDD. As with the
series termination resistor, the output strapping resistor
should be placed as close to the I/O pin as possible in order
to keep the interconnecting trace short. The trace from the
resistor to ground or VDD should be kept less than two
inches in length to prevent system noise coupling during
input logic sampling.
Figure 1. Input Logic Selection through Resistor Load Option
VDD
Series
Terminating
Resistor
10K Load
Option 1
10K Load
Option 0
Clock Load
RC7144
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