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参数资料
| 型号： | RC7144 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 14/16页 |
| 文件大小： | 61K |
| 代理商： | RC7144 |
PRODUCT SPECIFICATION
RC7144
7
Pr
eliminar
y
Infor
mation
I2C Register Operation
The RC7144 is programmed by writing 10 bytes
of eight bits each. See Table 2 for byte order.
Table 2. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit
Sequence
Byte Description
1
Slave
Address
11010010
Commands the RC7144 to accept the bits in Data Bytes 0-6 or internal
register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the RC7144
is 11010010. Register setting will not be made if the Slave Address is
not correct (or is for an alternate slave receiver).
2
Command
Code
Don’t Care
Unused by the RC7144, therefore, bit values are ignored (don’t care).
This byte must be included in the data write sequence to maintain
proper byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
3
Byte Count
Don’t Care
Unused by the RC7144, therefore, bit values are ignored (don’t care).
This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standard serial
communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
4
Data Byte 0
Refer to
Table 3
The data bits in these bytes set internal RC7144 registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to Table 5, Data Byte Serial Configuration Map.
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
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