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参数资料
| 型号： | RC7144 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 13/16页 |
| 文件大小： | 61K |
| 代理商： | RC7144 |
RC7144
PRODUCT SPECIFICATION
6
Pr
eliminar
y
Infor
mation
I2C Interface Information
The RC7144 features a two-pin, serial data interface that can
be used to congure internal register settings that control
particular device functions. Upon power-up, the RC7144 ini-
tializes with default register settings therefore, the use of this
serial data interface is optional. The serial interface is write-
only (to the clock chip) and is the dedicated function of
device pins SDA and SCL. In motherboard applications,
SDA and SCL are typically driven by two logic outputs of
the chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions. Table 1 summarizes the control functions of
the serial data interface.
Table 1. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output
Disable
Any individual clock output(s) can be
disabled. Disabled outputs are actively
held low.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock
outputs to unused PCI slots.
CPU Clock
Frequency Selection
Provides CPU/PCI frequency selections
other than the 100MHz provided upon
power-on. Frequency is changed in a
smooth and controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change
under normal system operation.
Spread Spectrum
Enabling
Turns spread spectrum on or off.
EMI reduction.
Output Tristate
Puts all clock outputs into a high
impedance state.
Production PCB testing.
Test Mode
All clock ouputs toggle in relation to X1
input, internal PLL is bypassed. Refer to
Table 6.
Production PCB testing.
Reserved
Reserved function for future device
revision or production device testing.
No user application. Register bit must be
written as 0.
RC7144 I2C Interface Write Sequence Example
MSB
1
12
34
5
6
7
8
A
1
2
38
A
1
2
8A
1
0
1
0
1
0
MSB
LSB
STOP
START
SDA
SCL
SDA
(ACK Signal
From Buffer Chip)
LSB
Slave Address (First Byte)
Signal from Motherboard Clock Chip
Command Code (2nd Byte)
Byte Count (3rd Byte)
Last Data Byte
Note:
Once the clock detects the start condition and its ADDRESS is matched, the clock chip will pull down the SDA at every 8th bit. The 8 bit data
from SDA is latched into the Buffer Chip when the ACK is generated. This ACK signal will continue as long as STOP condition is detected The
COMMAND CODE and BYTE COUNT is not used by the Buffer Chip.
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