参数资料
型号: RCPXA271FC0312
厂商: MARVELL SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 312 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 113/138页
文件大小: 1048K
代理商: RCPXA271FC0312
Part 2: Flash Device Operations
Flash Programming Operations
76
Intel PXA27x Processor Family Memory Subsystem
Status Register bit SR.7 indicates the programming status while the sequence executes. Commands
that can be issued to the programming partition during programming are Program Suspend, Read
Status Register, Read Device Identifier, CFI Query, and Read Array (this returns unknown data).
When programming has finished, SR.4 (when set) indicates a programming failure. If SR.3 is set,
the WSM could not perform the word programming operation because
F-VPP was outside of its acceptable limits. If SR.1 is set, the word programming operation
attempted to program a locked block, causing the operation to abort.
Before issuing a new command, the Status Register contents should be examined and then cleared
using the Clear Status Register command. Any valid command can follow, when word
programming has completed.
11.1.1
Flash Factory Word Programming
Factory word programming is similar to word programming in that it uses the same commands and
programming algorithms. However, factory word programming enhances the programming
performance with F-VPP = VPPH. This can enable faster programming times during factory
manufacturing processes. Factory word programming is not intended for extended use. See
Section 5.2, “Operating Conditions” on page 36 for limitations when F-VPP = VPPH.
Note:
When F-VPP = VPPL, the flash draws programming current from the F-VCC supply. If F-VPP is
driven by a logic signal, VPPL must remain above VPPL MIN to program the flash. When
F-VPP = VPPH, the flash draws programming current from the F-VPP supply. Figure 26, “Example
F-VPP Supply Connections” on page 80 shows examples of flash power supply configurations.
11.2
Flash Buffered Programming
The flash features a 32-word buffer to enable optimum programming performance. For Buffered
Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed
into the flash memory array in buffer-size increments. This can improve system programming
performance significantly over non-buffered programming.
When the Buffered Programming Setup command is issued. See Section 9.3, “Flash Command
Definitions” on page 66, Status Register information is updated and reflects the availability of the
write buffer. SR.7 indicates buffer availability: if set, the buffer is available; if cleared, the write
buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-
check SR.7. When SR.7 is set, the buffer is ready for loading. See Figure 54, “Flash Buffer
On the next write, a word count is written to the flash at the buffer address. This tells the flash how
many data words will be written to the buffer, up to the maximum size of the buffer.
On the next write, a flash start address is given along with the first data to be written to the flash
memory array. Subsequent writes provide additional flash addresses and data. All data addresses
must lie within the start address plus the word count. Optimum programming performance and
lower power usage are obtained by aligning the starting address at the beginning of a 32-word
boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will result in
doubling the total programming time due to refilling the buffer region.
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