参数资料
型号: RCPXA271FC0312
厂商: MARVELL SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 312 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 119/138页
文件大小: 1048K
代理商: RCPXA271FC0312
Part 2: Flash Device Operations
Flash Erase Operations
Intel PXA27x Processor Family Memory Subsystem
81
Flash Erase Operations
12
Flash erasing is performed on an individual block basis. An entire block is erased each time an
erase command sequence is issued, and only one block is erased at a time. When a block is erased,
all bits within that block read as logical ones. The following sections describe block erase
operations in detail.
12.1
Flash Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the address of
the target block to be erased. See Section 9.3, “Flash Command Definitions” on page 66. Next, the
Block Erase Confirm command is written to the address of the block to be erased. Erasing can
occur in only one partition at a time; all other partitions must be in a read state. If the flash is placed
in standby (F-CE# deasserted) during an erase operation, the flash continues to complete the erase
operation before entering standby.
Note:
F-VPP > VPPLK and the block must be unlocked (see Figure 56, “Flash Block Erase Flowchart” on
During a block erase, the flash Write State Machine (WSM) executes a sequence of internally-
timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory
array changes “logical-zeros” to “logical-ones.” Memory array bits can be changed to zeros only
The Status Register can be examined for block erase progress and errors by reading any address
within the partition that is being erased. The partition remains in the Read Status Register state
until another command is written to that partition. Issuing the Read Status Register command to
another partition address sets that partition to the Read Status Register state, allowing erase
progress to be monitored at that partition’s address. SR.0 indicates whether the addressed partition
or another partition is erasing. The partition’s Status Register bit SR.7 is set upon erase completion.
SR.7 indicates block erase status while the sequence executes. When the erase operation has
finished, Status Register bit SR.5 indicates an erase failure if set. SR.3 set would indicate that the
WSM could not perform the erase operation because F-VPP was outside of its acceptable limits.
SR.1 set indicates that the erase operation attempted to erase a locked block, causing the operation
to abort.
Before issuing a new command, the Status Register contents should be examined and then cleared
using the Clear Status Register command. Any valid command can follow once the block erase
operation has completed.
12.2
Flash Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows
data to be accessed from memory locations other than the one being erased. The Erase Suspend
command can be issued to any flash address; the corresponding partition is not affected. A block
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