参数资料
型号: RCPXA271FC0312
厂商: MARVELL SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 312 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 4/138页
文件大小: 1048K
代理商: RCPXA271FC0312
Part 3: LPSDRAM Operations
LPSDRAM Command and Operation
Intel PXA27x Processor Family Memory Subsystem
101
LPSDRAM Command and Operation
17
17.1
LPSDRAM No Operation / LPSDRAM Deselect
The No Operation / LPSDRAM Deselect command is used on a LPSDRAM that is selected
(D-CS# / R-DS# is low). It is also used to deselect the LPSDRAM by preventing new commands
from being executed. Operations already in progress are not affected.
17.2
LPSDRAM Active
The Active command is used to activate a row in particular bank for a subsequent read or write
access. The value of the bank D-BA[1:0] and the row address needs to be provided. The row
remains active until a precharge command is issued to the bank. A Precharge command must be
issued before opening a different row in the same bank.
More than one bank can be active at any time. A read or write command could be issued to that
row, subject to the tRCD specification. tRCD (min) should be divided by the clock period and
rounded up to the next whole number to determine the earliest clock edge after the active command
on which the read/write can be entered. A subsequent Active command to another row in the same
bank can only be issued after the previous row has been closed. The minimum time interval
between two successive active commands on the same bank is defined by tRC. The minimum time
interval between two successive active commands on the different banks is defined by tRRD. This is
illustrated in Figure 34 on page 104.
17.3
LPSDRAM Read Command
Read command is used to initiate a burst read to an active row. The value of D-BA[1:0] select the
bank and address inputs select the starting column location. The value of A11 determines whether
or not auto precharge is used. Output data appears on the data bus, subject to the logic level on the
D-DM[1:0] inputs two clocks earlier. D-DM[1:0] latency for read command is 2 clock cycles.
The burst length is set in the mode register. The starting column and bank address is provided along
with the auto precharge option. During read bursts, the starting valid data-out corresponding to the
starting column address will be available after CAS latency cycles after the read command. Each
subsequent data-out will be valid by the next positive edge of the clock. This is shown in Figure 35,
a read burst may be truncated by a subsequent read command. The first data from the new burst
follows either the last element of a completed burst or the last desired element of a longer burst that
is being truncated. The new read command can be issued as early as CL-1 cycles before the last
Figure 37 on page 105 shows random LPSDRAM access reads. These can be issued to the same or
different banks.
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