参数资料
型号: RCPXA272FC0520
厂商: MARVELL SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 520 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 35/138页
文件大小: 1048K
代理商: RCPXA272FC0520
Part 1: EMTS
Device Overview
Intel PXA27x Processor Family Memory Subsystem
13
Device Overview
2
The PXA27x processor memory subsystem device combines 128- or 256-Mbit Intel StrataFlash
memory die with or without 256-Mbit low-power SDRAM die on Intel stacked package. The
following section describes the PXA27x processor memory subsystem features, operation, and
characteristics of the flash and LPSDRAM devices.
2.1
Intel StrataFlash Memory Die
The flash die provides read-while-write or read-while-erase capability with density upgrades of
256-Mbit increments. The flash die provides high-performance at low voltage on a 16-bit data bus
and individually erasable memory blocks sized for optimum code and data storage.
The flash die contains one parameter partition and several main partitions. The flash memory
arrays are grouped into multiple 8-Mbit partition for 128-Mbit flash die, or 16-Mbit partitions for
256-Mbit flash die. By dividing the flash memory into partitions, program or erase operations can
take place simultaneously as read operation. Although each partition has write, erase, and burst
read capabilities, simultaneous operations are limited to write or erase in one partition while
reading in the another partition. Burst reads across partition boundaries are allow, but the burst
reads are not allow to cross into a partition that is busy in programming or erasing mode, or across
flash dies within the PXA27x processor memory subsystem. A new burst read operation must be
initiated when crossing these bondaries.
Upon initial power up or return from reset, the flash defaults to asynchronous page-mode read.
Configuring the Read Configuration Register (RCR) enables flash synchronous burst-mode reads.
In synchronous burst-mode, output data are synchronized with the memory bus clock signal.
In addition to the enhanced architecture and interface, the flash die incorporates technology that
enables fast factory program and erase operations. Designed for low-voltage systems, the flash
supports read operations with F-VCC at 1.8 volt, and erase and program operations with F-VPP at
1.8 V or 9.0 V. Buffered Enhanced Factory Programming (Buffered EFP) provides the fastest flash
array programming performance with F-VPP at 9.0 volt, which increases factory throughput. With
F-VPP at 1.8 V, F-VCC and F-VPP can be tied together for a simple, ultra-low power design. In
addition to voltage flexibility, a dedicated F-VPP connection provides complete data protection
when F-VPP is less than VPPLK.
A flash Command User Interface (CUI) is the interface between the PXA27x processor and all
internal operations of each selected flash die. An internal flash Write State Machine (WSM)
automatically executes, for example, the algorithms and timings necessary for block erase and
program. A Status Register indicates erase or program completion and any errors that may have
occurred.
An industry-standard flash command sequence invokes program and erase automation. Each erase
operation erases one block at a time. The Erase Suspend feature allows system interrupt to pause an
erase cycle to read or program data in another block in another partition. Program Suspend allows
system interrupt to pause programming to read other locations. The flash array is programmed in
16-bits increments.
相关PDF资料
PDF描述
RCPXA273FC0416 416 MHz, MICROPROCESSOR, PBGA336
RCPXA273FC0520 520 MHz, MICROPROCESSOR, PBGA336
RCPXA272FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0416 416 MHz, MICROPROCESSOR, PBGA336
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