参数资料
型号: RCPXA273FC0520
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 520 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 112/138页
文件大小: 1048K
代理商: RCPXA273FC0520
Part 2: Flash Device Operations
Flash Programming Operations
Intel PXA27x Processor Family Memory Subsystem
75
Flash Programming Operations
11
The flash supports three programming methods: Single-word programming (0x40/0x10), Buffered
Programming (0xE8, 0xD0), and Buffered Enhanced Factory Programming (Buffered EFP) (0x80,
programming commands issued to the flash.
To perform a write operation, both F-CE# and WE# are asserted while F-RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge of WE# or
F-CE#, whichever occurs first. Table 21, “Flash Command Bus Cycles” on page 65 shows the bus
cycle sequence for each of the supported flash commands, while Table 22, “Flash Command Codes
Specifications” on page 47 for signal-timing details.
Warning:
Write operations with invalid F-VCC and/or F-VPP voltages can produce spurious results and
should not be attempted.
Successful programming requires the addressed block to be unlocked. If the block is locked down,
F-WP# must be deasserted and the block must be unlocked before attempting to program the block.
Attempting to program a locked block causes a program error (SR.4 and SR.1 are set) and
termination of the operation. See Section 13, “Flash Security Modes” on page 83 for details on
locking and unlocking blocks.
11.1
Flash Word Programming
Word programming operations are initiated by writing the Word Program Setup command to the
flash (see Section 9.2, “Flash Bus Operations” on page 64). This is followed by a second write to
the flash with the address and data to be programmed. The partition accessed during both write
cycles outputs Status Register data when read. The partition accessed during the second cycle (the
data cycle) of the program command sequence is the location where the data is written. See
Programming can occur in only one partition at a time; all other partitions must be in a read state or
in erase suspend. F-VPP must be above VPPLK, and within the specified VPPL value.
During programming, the flash Write State Machine (WSM) executes a sequence of internally-
timed events that program the desired data bits at the addressed location, and verifies that the bits
are sufficiently programmed. Programming the flash memory array changes “ones” to “zeros.”
Flash array bits that are zeros can be changed to ones only by erasing the block. See Section 12,
The flash Status Register can be examined for programming progress and errors by reading any
address within the partition that is being programmed. The partition remains in the Read Status
Register state until another command is written to that partition. Issuing the Read Status Register
command to another partition address sets that partition to the Read Status Register state, allowing
programming progress to be monitored at that partition’s address.
相关PDF资料
PDF描述
RCPXA272FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0416 416 MHz, MICROPROCESSOR, PBGA336
RD151TS3312ARPH0 20 MHz, OTHER CLOCK GENERATOR, PDSO8
RD151TS3314ARPH0 80 MHz, OTHER CLOCK GENERATOR, PDSO8
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