参数资料
型号: RCPXA273FC0520
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 520 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 6/138页
文件大小: 1048K
代理商: RCPXA273FC0520
Part 3: LPSDRAM Operations
LPSDRAM Command and Operation
Intel PXA27x Processor Family Memory Subsystem
103
17.6
LPSDRAM Deep Power-Down
The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage
generators inside the LPSDRAM are stopped and all memory data are lost in this mode. To enter
the DPD mode, all banks must be precharged, prior to the DPD command. To exit this mode, the
D-CKE is taken high after the clock is stable.
17.7
LPSDRAM Clock Suspend
This mode occurs when a column access or burst is in progress, and D-CKE is set low. The internal
clock gets suspended freezing the LPSDRAM logic. Any command or data present on the input
pins at the time of suspended internal clock is ignored. The output data on the pins stays frozen.
This mode is exited by setting D-CKE high, which results in resumption of the operation. Figure 46
on page 108 shown Clock suspend during a Write burst and Figure 47 on page 109 shows a clock
suspend during a Read burst.
17.8
LPSDRAM Precharge
The Precharge is used to deactivate an active row in a particular bank or active row in all banks.
The banks will be available for row access after a specified time (tRP) after the Precharge command
is issued. If one bank is to precharged, the particular bank address needs to be addressed. If all
banks are to be precharged, A11 should be set high along with the Precharge command.
17.9
LPSDRAM Auto Precharge
Auto Precharge is accomplished when A11 is high, to enable auto precharge in conjunction with a
specific read or write command. This precharges the row after the read or write burst is complete.
Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst.
Another command to the same bank must not be issued until the precharge time (tRP) is completed.
Auto precharge does not apply in full-page burst mode. Auto precharge is non- persistent.
17.10
LPSDRAM Concurrent Auto Precharge
If an access command with Auto Precharge enabled is being executed, it can be interrupted by
another access command.
Figure 48 on page 109 shows a Read with Auto Precharge to Bank n, interrupted by a Read
(with or without Auto precharge) to bank m. The Read to bank m will interrupt the Read to
Bank n, CAS# latency later. The precharge to bank n will begin when the Read to bank m is
registered.
Figure 49 on page 109 shows a Read with Auto Precharge to Bank n, interrupted by a Write
(with or without Auto precharge) to bank m. The precharge to bank n will begin when the
Write to bank m is registered. D-DM[1:0] should be set high 2 clock before the Write
command to prevent bus contention.
相关PDF资料
PDF描述
RCPXA272FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0416 416 MHz, MICROPROCESSOR, PBGA336
RD151TS3312ARPH0 20 MHz, OTHER CLOCK GENERATOR, PDSO8
RD151TS3314ARPH0 80 MHz, OTHER CLOCK GENERATOR, PDSO8
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