参数资料
型号: RCPXA273FC0520
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 520 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 130/138页
文件大小: 1048K
代理商: RCPXA273FC0520
Part 2: Flash Device Operations
Flash Dual-Operation Considerations
Intel PXA27x Processor Family Memory Subsystem
91
The processor provides an address to the flash.
The processor then provides data to the flash.
The flash in turn binds the received data with the received address. When operating synchronously
(RCR.15 = 0), the address of a write cycle may be provided to the flash by the first active clock
edge with ADV# low, or rising edge of ADV# as long as the applicable cycle separation conditions
are met between each cycle.
If neither a clock edge nor a rising ADV# edge is used to provide a new address at the beginning of
a write cycle (the clock is stopped and ADV# is low), the address may also be provided to the flash
by holding the address bus stable for the required amount of time (W5, tAVWH) before the rising
WE# edge.
Alternatively, the host may choose not to provide an address to the flash during subsequent write
cycles (if ADV# is high and only F-CE# or WE# is toggled to separate the prior cycle from the
current write cycle). In this case, the flash will use the most recently provided address from the
host.
For representation of these timings see:
14.2.5
Flash Read During Flash Buffered Programming
The multi-partition architecture of the flash allows background programming (or erasing) to occur
in one partition while data reads (or code execution) take place in another partition.
To perform a read while buffered programming operation, first issue a Buffered Program set up
command in a partition. When a read operation occurs in the same partition after issuing a setup
command, Status Register data will be returned, regardless of the read mode of the partition prior to
issuing the setup command.
To read data from a block in other partition and the other partition already in read array mode, a
new block address must be issued. However, if the other partition is not already in read array mode,
issuing a read array command will cause the buffered program operation to abort and a command
sequence error would be posted in the Status Register.
Simultaneous read-while-Buffered EFP is not supported.
14.3
Simultaneous Flash Operation Restrictions
Since the flash supports simultaneous read from one partition while programming or erasing in
another partition, certain features like the Protection Registers and CFI Query data have special
requirements with respect to simultaneous operation capability. (Table 26 provides details on
restrictions during simultaneous operations.)
相关PDF资料
PDF描述
RCPXA272FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0416 416 MHz, MICROPROCESSOR, PBGA336
RD151TS3312ARPH0 20 MHz, OTHER CLOCK GENERATOR, PDSO8
RD151TS3314ARPH0 80 MHz, OTHER CLOCK GENERATOR, PDSO8
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