参数资料
型号: RCPXA273FC0520
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 520 MHz, MICROPROCESSOR, PBGA336
封装: 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数: 91/138页
文件大小: 1048K
代理商: RCPXA273FC0520
Part 1: EMTS
Power and Reset Specifications
56
Intel PXA27x Processor Family Memory Subsystem
Table 17.
Flash Reset Timing
8.5
Flash Power Supply Decoupling
Flash memory device require careful power supply decoupling. Three basic power supply current
considerations are require: 1) Standby current levels, 2) Active current levels, and 3) Transient
peaks produced when F-CE# and OE# are asserted and deasserted.
When the flash is accessed, many internal conditions change. Transient current magnitudes depend
on the device outputs’ capacitive and inductive loading. Two-line control and correct decoupling
capacitor selection suppress transient voltage peaks. Because Intel StrataFlash memory draws its
power from F-VCC, F-VPP, and VCCQ, therefore each power connection should have a 0.1 F
ceramic capacitor connected to a corresponding ground connection (e.g.,VCCQ to VSS). High-
frequency, inherently low-inductance capacitors should be placed as close as possible to package
leads.
It is recommended, for every eight devices used in the system, a 4.7 F electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is meant to
overcome voltage droop caused by PCB trace inductance.
Nbr.
Symbol
Parameter
Min
Max
Unit
Notes
P1
tPLPH
F-RST# pulse width low
100
ns
1,2,3,5
P2
tPLRH
F-RST# low to device reset during erase
25
s
3,4,5
F-RST# low to device reset during program
25
3,4,5
P3
tVCCPH
F-VCC Power valid to F-RST# de-assertion
(high)
60
1,3,5
NOTES:
1. The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed.
2. If F-RST# is tied to the F-VCC supply, the flash will not be ready until tVCCPH and after F-VCC ≥ F-VCC MIN.
3. If F-RST# is tied to any pin or signal with VCCQ voltage levels, the F-RST# input voltage must not exceed
F-VCC until F-VCC ≥ F-VCC MIN.
4. Reset completes within tPLPH if F-RST# is asserted while no erase or program operation is executing.
5. Sampled, but not 100% tested.
Figure 23.
Flash Reset Operation Waveforms
F-V
CC
F-RST# [P]
V
IH
V
IL
F-RST# [P]
V
IH
V
IL
F-RST# [P]
V
IH
V
IL
P2
P3
P2
P1
R5
0 V
Abort
Complete
Abort
Complete
F-V
CC
(A) Reset during read mode
(B) Reset during program or
block erase P1 < P2
(C) Reset during program or
block erase P1 > P2
(D) F-VCC Power-up to
F-RST# high
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