参数资料
| 型号： | RDK-236 |
| 厂商： | Power Integrations |
| 文件页数： | 4/30页 |
| 文件大小： | 0K |
| 描述： | KIT REF DESIGN PFS714EG |
| 标准包装： | 1 |
| 系列： | HiperPFS™ |
| 主要目的： | 电源管理，功率因数校正 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | PFS714EG |
| 主要属性： | 347W，370 ~ 390V 输出，90 ~ 264VAC 输入 |
| 已供物品： | 板 |
| 其它名称： | 596-1418 |
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PFS704-729EG
Pin Functional Description
VOLTAGE MONITOR (V) Pin:
The V pin is tied to the rectified AC rail through an external
resistor. Internal circuitry detects the peak of the input line
voltage which resembles a full-wave rectified waveform. The
rectified high-voltage bus is connected directly to the V pin
voltage through a large resistor (4 M W for PFS70x and PFS71x;
9 M W for PFS72x) to minimize power dissipation and standby
power consumption. A small ceramic capacitor (0.1 m F for
PFS70x and PFS71x; 0.047 m F for PFS72x) is required from the
VOLTAGE MONITOR pin to SIGNAL GROUND pin to bypass
any switching noise present on the rectified bus. This pin also
features both brown-in and brown-out protection.
SIGNAL GROUND (G) Pin:
Discrete components used in the feedback circuit, including
loop compensation, decoupling capacitors for the supply (VCC)
and line-sense (V) must be referenced to the G pin. The
SIGNAL GROUND pin must not be tied to the SOURCE pin .
SOURCE (S) Pin:
This pin is the source connection of the power switch.
DRAIN (D) Pin:
This is the tab and drain connection of the internal power switch.
E Package (eSIP-7G)
FEEDBACK (FB) Pin:
The FEEDBACK pin is high input-impedance reference terminal
that connects to a feedback resistor network. This pin will also
feature fast overvoltage and undervoltage detection circuitry
that will disengage the internal power MOSFET in the event of a
Exposed Metal (On Edge)
Internally Connected
to GROUND Pin
Exposed Metal
(On Edge)
Internally
Connected to
DRAIN Pin
system fault. A 10 nF capacitor is required between the
FEEDBACK to SIGNAL GROUND pins; this capacitor must be
placed very close to the device on the PCB to bypass any
switching noise. This pin is also used for loop compensation.
BIAS POWER (VCC) Pin:
This is a 10-12 VDC bias supply used to power the IC. The bias
voltage must be externally clamped to prevent the VCC pin
1 23 4 5
7
7
54 3 2 1
Exposed Pad
(Backside)
Internally
Connected to
DRAIN Pin
(see eSIP-7G
Package
Drawing)
PI-5334-083110
from exceeding 15 VDC.
Figure 2.
Pin Configuration.
VOLTAGE MONITOR (V)
BIAS POWER (VCC)
DRAIN (D)
INPUT
LINE INTERFACE
Peak
Detector
INTERNAL
SUPPLY
+
-
V CC+
OTP
M ON I VPK
Input UV
(I UV- /I UV+ )
6 V
Input Voltage
Emulation
+
-
“Off-time derived with
constant Volt-Sec
V O -V IN
C INT
SOFT
START
7 kHz
Filter
(V OFF = 0.8 V for PFS723-729). I Frequency
Internal
Error-Amplifier
FEEDBACK (FB)
FB OV -
FB UV /
Comparator
Latch FB OV/UV
V OFF
V E
V OFF is a function of the error-voltage (V E ) and is used to reduce the average
operating frequency as a function of output power for increased efficiency
(PFS704-716).
VPK Slide
Transconductance V
E
Reference
V REF
+ 1 kHz
Filter
-
M ON is the switch current
sense scale factor which
is function of peak line
+ voltage derived from I VIN
Fast OV M ON I S
Comparator
FB OFF
+
Input UV
-
+
Comparator OTP
+
-
TIMER
SUPERVISOR
The internal derived error-voltage (V E )
regulates the output voltage
C INT
V CC
Driver
LEB
OCP
Sense
FET
I S
+
I OCP
-
Power
MOSFET
-
UV Comparator
SIGNAL GROUND (G)
SOURCE (S)
PI-5333-113010
Figure 3.
4
Rev. F 12/12
Functional Block Diagram.
www.powerint.com
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