参数资料
| 型号： | RDK-236 |
| 厂商： | Power Integrations |
| 文件页数： | 6/30页 |
| 文件大小： | 0K |
| 描述： | KIT REF DESIGN PFS714EG |
| 标准包装： | 1 |
| 系列： | HiperPFS™ |
| 主要目的： | 电源管理，功率因数校正 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | PFS714EG |
| 主要属性： | 347W，370 ~ 390V 输出，90 ~ 264VAC 输入 |
| 已供物品： | 板 |
| 其它名称： | 596-1418 |
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PFS704-729EG
1.2
1
0.8
Soft-Start
Check
Sequence
0.6
0.4
Is
V CC >
V CC+
NO
Apply
6 mA V Pin
Current Sink
Detect Input
Voltage Peak
0.2
YES
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Apply 0.5 A
on FB to
Check Open FB
Is V FB > FB OFF
NO
Start
Converter
Normalized to Peak Power Rating
Figure 5.
Typical Normalized Output Voltage Characteristics as Function of
Normalized Peak Load Rating
Is
V FB > FB OFF
and
V FB < FB OV
NO
YES
Remove
6 mA V Pin
Current Sink
Slew Power-Limit
Over Soft-Start
Duration
YES
V CC+
t START-DELAY
Is I V > I UV+
NO
YES
PI-5337-110910
t SOFT
~5 V
Figure 7.
Start-Up Sequence.
threshold the V pin holds the 6 mA current sink indefinitely until
t
PI-5336-110810
the FEEDBACK pin is above the FB OFF . If the FEEDBACK pin
voltage is above FB OFF , the IC releases the current source and
resumes with normal soft-start and operation. Figure 7
illustrates this sequence.
Figure 6.
Power Limit Soft-Start Function.
Timing Supervisor and Operating Frequency Range
NPN and PNP transistor are tied between the output voltage
divider resistors to limit the maximum overshoot and under-
shoot during a load transient response. To reduce switch and
output diode current stress at start-up, the HiperPFS slews the
internal error-voltage from zero to its steady-state value at
start-up. Figure 6 illustrates the relative relationship between
the application of V CC and power limit soft-start function through
the internal error-voltage.
The error-voltage has a controlled slew rate of 0.25 V/ms at
start-up, corresponding to the t SOFT time duration for a full scale
error voltage of 5 V.
The beginning of soft-start is gated by the V CC+ , I UV+ and
FEEDBACK pin voltage thresholds in the sequence described
below. Once the applied V CC is above the V CC+ threshold, the
sensed V pin current is above I UV+ and the feedback pin voltage
is above FB OFF , the IC applies a ~6 mA current sink through the
VOLTAGE MONITOR pin and checks that the FEEDBACK pin
voltage is still above the FB OFF threshold. This checks to ensure
that the FEEDBACK and V pins are not shorted together. In the
event that the FEEDBACK pin voltage is below the FB OFF
6
Rev. F 12/12
Since the controller is expected to operate with a variable
switching frequency over the line frequency half-cycle, typically
spanning a range of 24 – 95 kHz, the controller also features a
timing supervisor function which monitors and limits the
maximum switch on-time and off-time as well as ensures a
minimum cycle off-time. The timer supervisor limits the normal
operating frequency range for loads in excess of 10% of the
device peak power rating.
Figure 8a shows the typical half-line frequency profile of the
device switching frequency as a function of input voltage at
peak load conditions. Figure 8b shows for a given line condition
the effect of EcoSmart to the switching frequency as a function
of load (PFS704-716). The switching frequency is not a function
of boost choke inductance.
EcoSmart
The PFS704-716 controllers includes an EcoSmart mode
wherein the internal error signal (V E ) is used to detect the
converter output power. Since the internal error-signal is
directly proportional to the output power, this signal level is used
to set the average switching frequency as a function of output
power. The off-time integrator control reference (V OFF ) is
www.powerint.com
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