Low Voltage Intel Xeon Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
Datasheet
17
2.5.1
Mixing Processors
Intel only supports those processor combinations operating with the same system bus frequency,
core frequency, VID settings, and cache sizes. Not all operating systems may support multiple
processors with mixed frequencies. Intel does not support or validate operation of processors with
different cache sizes. Mixing processors of different steppings but the same model (as per CPUID
instruction) is supported, and is outlined in the Intel Xeon Processor Specification Update.
Additional details are provided in AP-485, the Intel Processor Identification and the CPUID
Instruction application note.
Unlike previous Intel Xeon processors, the Low Voltage Intel Xeon processor does not sample the
pins IGNNE#, LINT[0]/INTR, LINT[1]/NMI, and A20M# to establish the core to system bus ratio.
Rather, the processor runs at its tested frequency at initial power-on. When the processor needs to
run at a lower core frequency, as must be done when a higher speed processor is added to a system
that contains a lower frequency processor, the system BIOS is able to effect the change in the core
to system bus ratio.
2.6
Voltage Identification
The VID specification for the processor is defined in this datasheet, and is supported by power
delivery solutions designed according to the Dual Intel Xeon Processor Voltage Regulator
Down (VRD) Design Guidelines, VRM 9.0 DC-DC Converter Design Guidelines, and VRM 9.1
DC-DC Converter Design Guidelines. The minimum voltage is provided in
Table 7, and varies
with processor frequency. This allows processors running at a higher frequency to have a relaxed
minimum voltage specification. The specifications have been set such that one voltage regulator
design may work with all supported processor frequencies.
Note that the VID pins may drive valid and correct logic levels when the Intel
Xeon processor is
provided with a valid voltage applied to the VID_VCC pins. VID_VCC must be correct and stable
prior to enabling the output of the VRM that supplies VCC. Similarly, the output of the VRM
must be disabled before VID_VCC becomes invalid. Refer to Figure 16 for details. The processor uses five voltage identification pins, VID[4:0], to support automatic selection of
processor voltages.
Table 4 specifies the voltage level corresponding to the state of VID[4:0]. In
this table, a 1 refers to a high voltage and a 0 refers to low voltage level. When the processor socket
is empty (VID[4:0] = 11111), or the VRD or VRM cannot supply the voltage that is requested, it
must disable its voltage output. For further details, see the Dual Intel XeonTM Processor Voltage
Regulator Down (VRD) Design Guidelines, or VRM 9.0 DC-DC Converter Design Guidelines or
the VRM 9.1 DC-DC Converter Design Guidelines.