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| 型号： | RK80532EC056512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2400 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO PGA-604 |
| 文件页数： | 16/102页 |
| 文件大小： | 2349K |
| 代理商： | RK80532EC056512 |
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Low Voltage Intel Xeon Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
20
Datasheet
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and may
become active at any time during the clock cycle. Table 5 identifies which signals are common
clock, source synchronous and asynchronous.
Table 5.
System Bus Signal Groups
Signal Group
Type
Signals1
AGTL+ Common Clock Input
Synchronous to BCLK[1:0]
RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
BR0#
AGTL+ Source Synchronous
I/O
Synchronous to assoc.
strobe
AGTL+ Strobes
Synchronous to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Asynchronous GTL+ Input
Asynchronous
Asynchronous GTL+ Output4
Asynchronous
FERR#, IERR#, THERMTRIP#
Asynchronous GTL+ Input/
Output9
Asynchronous
PROCHOT#
System Bus Clock
Clock
BCLK1, BCLK0
TAP Input2
Synchronous to TCK
TCK, TDI, TMS, TRST#
TAP Output2
Synchronous to TCK
TDO
Power/Other
BSEL[1:0], COMP[1:0], GTLREF, ODTEN,
Reserved, SKTOCC#, TESTHI[6:0],VID[4:0],
VCC, VCCA, VCCIOPLL, VSSA, VSS, VCCSENSE,
VSSSENSE, PWRGOOD, THERMDA,
THERMDC. VID_VCC
NOTES:
1. Refer to Section 5.2 for signal descriptions.
2. These AGTL+ signal groups are not terminated by the processor. Refer the ITP700 Debug Port Design
Guide and corresponding Design Guide for termination requirements and further details.
3. The Low Voltage Intel Xeon processor utilizes only BR0# and BR1#. BR2# and BR3# are not driven by
the processor but must be terminated to V
CC. For additional details regarding the BR[3:0]# signals, see
Section 5.2 and Section 7.1 and the appropriate Platform Design Guidelines.
4. These signal groups are not terminated by the processor. Refer to the appropriate platform design
guidelines and the ITP700 Debug Port Design Guide for termination recommendations.
5. The volume on these pins during active-to-inactive edge of RESET# determines the multiplier that the
Phase Lock Loop (PLL) will use for internal core clock
6. The value of these pins during the active-to-inactive edge of RESET# to determine processor configuration
options. See Section 7.1 for details.
7. These signals may be driven simultaneously by multiple agents (wired-OR).
8. VID_VCC is required for correct operation of the Low Voltage Intel
Xeon Processor. Refer to Figure 16
for details.
9. It is an output only on the 1.60 GHz Low Voltage Intel Xeon processor with CPUID of 0F27h.
Signals
Associated Strobe
REQ[4:0]#,A[16:3]#
ADSTB0#
A[35:17]#
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RK80532EE056512 SL74T | 制造商:Intel 功能描述: |
| RK80532EE056512S L74T | 制造商:Intel 功能描述:MPU Xeon? Processor 64-Bit 0.13um 2.4GHz 604-Pin FCmPGA2 制造商:Intel 功能描述:PRESTONIA; MPU XEON NETBURST 64BIT 0.13UM 2.4GHZ 604PIN - Trays |
| RK80532EE056512SL74T | 功能描述:IC XEON LV 2.4GHZ 604FC-MPGA-2P RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| RK80532KE056512 | 制造商:Intel 功能描述:OVERLAND DATA BOND - Trays 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RK80532KE056512S L6GD | 功能描述:IC XEON 2.4GHZ INT-MPGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
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