
Low Voltage Intel Xeon Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz
Datasheet
25
.
VRBM
Ringback
Margin
0.200
N/A
V
VTM
Threshold
Margin
VCROSS - 0.100
N/A
VCROSS + 0.100
V
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
falling edge of BCLK1.
3. VHavg is the statistical average of the VH measured by the oscilloscope.
4. Overshoot is defined as the absolute value of the maximum voltage.
5. Undershoot is defined as the absolute value of the minimum voltage.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge
Ringback and the maximum Falling Edge Ringback.
7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis.
8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
9. VHavg can be measured directly using “Vtop” on Agilent* scopes and “High” on Tektronix* scopes.
10.VCROSS is defined as the total variation of all crossing voltages as defined in note 2.
Table 9.
AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
VIH
Input High Voltage
1.10 * GTLREF
VCC
V
VIL
Input Low Voltage
0.0
0.90 * GTLREF
V
VOH
Output High Voltage
N/A
VCC
V
IOL
Output Low Current
N/A
VCC /
(0.50 * RTT_min + RON_min)
= 50
mA
IHI
Pin Leakage High
N/A
100
A
ILO
Pin Leakage Low
N/A
500
A
RON
Buffer On Resistance
7
11
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. VIH is defined as the minimum voltage level at a receiving agent that may be interpreted as a logical high
value.
3. VIL is defined as the maximum voltage level at a receiving agent that may be interpreted as a logical low
value.
4. VIH and VON may experience excursions above VCC. However, input signal drivers must comply with the
signal quality specifications in Chapter 3.0.
5. Refer to the Low Voltage Intel
Xeon Processor Signal Integrity Models for I/V characteristics.
6. The VCC referred to in these specifications refers to instantaneous VCC.
7. VOL_MAX of 0.450 V is ensured when driving into a test load as indicated in Figure 4, with RTT enabled. 8. Leakage to VCC with pin held at 300 mV.
9. Leakage to VSS with pin held at VCC.
Table 8.
System Bus Differential BCLK Specifications (Sheet 2 of 2)