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参数资料
型号： RN80532KC041512
厂商： INTEL CORP
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 2000 MHz, MICROPROCESSOR, CPGA603
封装： Interposer, Micro, PGA-603
文件页数： 115/129页
文件大小： 1640K
代理商： RN80532KC041512
Intel Xeon Processor with 512 KB L2 Cache
86
Datasheet
BR0#
BR[1:3]#1
I/O
I
BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The
BREQ[3:0]# signals are interconnected in a rotating manner to individual processor
pins. BR2# and BR3# must not be utilized in a dual processor platform design. The
table below gives the rotating interconnect between the processor and bus signals
for dual processor systems.
During power-on configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition
of RESET#. The pin which the agent samples asserted determines it’s agent ID.
These signals do not have on-die termination and must be terminated at the
end agent. See the appropriate platform design guidelines for additional
information.
1,4
BSEL[1:0]
O
These output signals are used to select the front side bus frequency. A BSEL[1:0] =
“00” will select a 100 MHz bus clock frequency. The frequency is determined by the
processor(s), chipset, and frequency synthesizer capabilities. All front side bus
agents must operate at the same frequency. Individual processors will only operate
at their specified front side bus (FSB) frequency.
On baseboards which support operation only at 100 MHz bus clocks these signals
can be ignored. On baseboards employing the use of these signals, a 1 K
pull-up
resistor be used.
See Table 2 “Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]” on
page 17 for output values.
COMP[1:0]
I
COMP[1:0] must be terminated to VSS on the baseboard using precision resistors.
These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate
platform design guidelines and Table 13 for implementation details.
Table 41. Signal Definitions (Page 3 of 10)
Name
Type
Description
Notes
BR[1:0]# Signals Rotating Interconnect, dual processor system
During power-up configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of
RESET#. The pin on which the agent samples an active level determines its agent
ID. All agents then configure their pins to match the appropriate bus signal protoco
as shown below.
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BR0#
BR1#
BREQ1#
BR1#
BR0#
BR[1:0]# Signal Agent IDs
BR[1:0]# Signals Rotating
Interconnect, dual processor system
Agent ID
BR0#
0
BR1#
1
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相关代理商/技术参数
参数描述
RN80532KC041512 SL5Z9 制造商:Intel 功能描述:MPU XEON 0.13UM 2GHZ 603-PIN UFCBGA - Trays
RN80532KC041512 SL6EM 制造商:Intel 功能描述:MPU XEON 0.13UM 2GHZ 603-PIN UFCBGA - Trays
RN80532KC041512S L5Z9 制造商:Intel 功能描述:MPU Xeon? Processor 0.13um 2GHz 603-Pin uFCBGA
RN80532KC041512S L6W6 制造商:Intel 功能描述:MPU Xeon? Processor 0.13um 2GHz 603-Pin uFCBGA
RN80532KC041512SL6EM 功能描述:IC MPU XEON 1.5V 2.0GHZ 603-INT3 RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘
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