参数资料
型号: RTC-62423A-3
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO24
封装: SOP-24
文件页数: 10/24页
文件大小: 195K
代理商: RTC-62423A-3
RTC - 62421 / 62423
Page - 15
MQ152-05
Read when the HOLD bit is not used (2)
Read using an interrupt
Timer (*3)
NO
YES
Set the CE register
Reg.E
t
ITRPT/STND
MASK
0
1
0 or 1
**10B
1
0
(*2)
0 or 1
From previous process
Setting completed
Operation
IRQ FLAG
0
Read the required digit data
Read the IRQ FLAG bit
IRQ FLAG bit = 0?
To next process
NO
YES (incrementation from RTC)
Reg.E
t
ITRPT/STND
MASK
0
1
0 or 1
**10B
1
0
(*2)
From previous process
Set the CE register
0 or 1
Interrupt generation
Setting completed
Operation
Read the IRQ FLAG bit
IRQ FLAG bit = 0?
Interrupt generation
from other device
Timer (*3)
Read the required digit data
IRQ FLAG
Return from interrupt processing
0
Clear the IRQ FLAG bit to
enable the next interrupt
(*2) Setting of interrupt generation frequency by the t1 and t0 bits
Interrupt frequency
t1 setting
t0 setting
Every second
0
1
Every minute
1
0
Every hour
1
(*3) Timer wait times
Timer mode
Timer wait time
12-hour clock
35
s
24-hour clock
3
s
3. Write to 30-second ADJ bit
The 30-seconds ADJ function is enabled by writing 1 to the 30-seconds ADJ bit. Note that the counter registers (S1 to W) cannot
be accessed for 125
s after this write. Therefore, follow one of the procedures shown below to use this function.
START
END
NO
YES
30-seconds ADJ bit
1
Read the 30-seconds ADJ bit
30-seconds ADJ bit = 0?
Wait 125
s
or
START
END
NO
YES
1
30-seconds ADJ bit
Read the 30-seconds ADJ
30-seconds ADJ bit = 0?
Note
The quartz crystal could be damaged if subjected to excessive shock. If the quartz crystal should stop operating for such a reason,
the timer within the RTC will stop. While the quartz crystal is operating, the BUSY bit is automatically reset every 190 s and the 30-
seconds ADJ bit, every 125
s, but this automatic reset cannot be done if the oscillation stops. Therefore, in such a status, it is no
longer possible to escape from the BUSY bit status check loop shown in subsection 2 above or the 30-seconds ADJ bit status check
loop shown in subsection 3 above, and you should consider backing up the system. To design a fail-safe system, provide an escape
from the loop to a procedure that can process such an error if the loop is repeated for more than 0.5 to 1.0 ms.
相关PDF资料
PDF描述
RTC-62423B-0 REAL TIME CLOCK, PDSO24
RTC-72421A 0 TIMER(S), REAL TIME CLOCK, PDIP18
RTC-72421B 0 TIMER(S), REAL TIME CLOCK, PDIP18
RTC-72423A-0 0 TIMER(S), REAL TIME CLOCK, PDSO24
RTC-72423B-0 REAL TIME CLOCK, PDSO24
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