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参数资料
| 型号： | RTC-62423A-3 |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封装： | SOP-24 |
| 文件页数： | 2/24页 |
| 文件大小： | 195K |
| 代理商： | RTC-62423A-3 |
RTC - 62421 / 62423
Page - 7
MQ152-05
3. Functions of register bits (overview)
Bit name
Function
* mark
Not used. Writing to this bit has no effect; reading it always returns 0.
Seconds-to-year digits All written in BCD code.
Day-of-the-week digit
This is a septal (base 7) counter that increments each time the day digits are incremented. It counts from 0 to 6. Since the
value in the counter bears no relationship to the day of the week, the user can choose the coding that relates the counter value
to the day of the week. The following is just one example of this relationship:
01
2
3
45
6
Count
Day
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
PM /AM
The PM/AM bit is 1 for p.m. times; 0 for a.m. times. This bit is valid only for 12-hour-clock mode (when the 24/12 bit is 0); in
24-hour-clock mode (when the 24 /12 bit is 1), this bit is always 0.
30-seconds ADJ
Writing 1 to this bit executes a 30-seconds correction.
IRQ FLAG
The IRQ FLAG bit is set to 1 when an interrupt request is generated in interrupt mode. Writing 0 to this bit clears it. Note that it
is possible to write 1 to this bit, but this will have no effect.
In fixed-period pulse output mode, this bit is at 1 while the pulse output is active (while the STD.P pin output is low), and is
automatically cleared when pulse output ends. Writing 0 to this bit while pulse output is active forcibly cancels the pulse
output.
BUSY
Use the BUSY bit when accessing data in the S1 to W registers. This bit is set to 1 during the incrementation cycle of the S1
to W registers, and is set to 0 otherwise. When the BUSY bit is 1, access to the S1 to W registers is inhibited.
Note that the HOLD bit must also be used when accessing the S1 to W registers. The BUSY bit is always 1 when the HOLD
bit is 0.
There is no need to check the BUSY bit when accessing the control registers (CD, CE, and CF).
HOLD
When 1 has been written to the HOLD bit, the status of the BUSY bit can be checked. While the HOLD bit is 1, any incre-
mentation of the digits is held just once. (The incrementation is held only once, even if the HOLD bit remains at 1 for two or
more seconds.)
Clear the HOLD bit to 0 by forcing the CS1 pin low.
t1, t0
These bits set the timing for fixed-period pulse output and interrupts (1/64 seconds, 1 second, 1 minute, or 1 hour).
ITRPT /STND
The ITRPT /STND bit sets fixed-period pulse output mode and interrupt mode. Write 1 to this bit to set interrupt (ITRPT)
mode; when write 0 to it to set pulse output (STND) mode.
MASK
The MASK bit disables fixed-period pulse output and interrupts. Write 1 to this bit to mask and inhibit these modes; write 0 to it
to enable these modes.
TEST
The TEST bit is used by EPSON for test purposes. Operation cannot be guaranteed if 1 is written to this bit, so make sure that
it is set to 0 during power-on initialization.
24 /12
The 24 /12 bit switches between 24-hour clock and 12-hour clock. Write 1 to this bit to set 24-hour mode; write 0 to it to set 12-
hour mode. When the 24/12 bit is set, both the timer registers and the timer mode must be reset to match. Note that the h20
bit of the H10 register is never set to 1 by the timer but it can be written to. To avoid timer errors, always keep the h20 bit at 0
in 12-hour clock mode.
In the setting of the timer mode, it is necessary to set the RESET bit to 1 then 0 after the 24/12 bit is set.
STOP
The STOP bit sets an inhibition on clock operation in 8192-Hz steps which are divider of the 1-second signal from the RTC's
internal 32,768-Hz oscillation source. The clock is inhibited when the STOP bit is 1, and released again when it becomes 0.
The internal oscillation circuit continues to operate even when the STOP bit is 1.
RESET
The RESET bit resets the part of the counter that is below a seconds. Write 1 to this bit to reset; 0 to release the reset.
If the clock mode has been affected by the setting of the 24/12 bit, it is necessary to set the RESET bit to 1 then 0.
RESET bit is cleared to 0, by a CS1 falling to low level.
4. Setting the fixed-period pulse output mode and interrupt mode
Mode
MASK
ITRPT/STND ITRPT/STND
STD.P pin
Setting of fixed-period output timing
Fixed-period pulse output mode
0
t1 bit
0
1
Interrupt mode
0
1
Set to 1
when
active
Set low when
active
t0 bit
0
1
0
1
Fixed-period pulse output
inhibited
1
0 or 1
"0"
Open-circuit
Output
period
1/64 s
1 s
1 min
1 hour
5. Resetting the fixed-period pulse output mode and interrupt mode
Mode
IRQ FLAG
STD.P pin
Write 0
Reset immediately after the write
(1"
→"0")
Reset immediately after the write
(low
→ open-circuit)
Fixed-period pulse output mode
MASK=0
ITRPT /STND=0
No write
Automatically returned by the set
period
("1"
→"0")
Automatically returned by the set
period (low
→ open-circuit)
Write 0
Reset immediately after the write
("1"
→"0")
Reset immediately after the write
(low
→ open-circuit)
Interrupt mode
MASK=0
ITRPT /STND=1
No write
The interrupt request continues, with no reset. The next interrupt is
ignored.
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| RTC-72421B | 0 TIMER(S), REAL TIME CLOCK, PDIP18 |
| RTC-72423A-0 | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| RTC-72423B-0 | REAL TIME CLOCK, PDSO24 |
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